myfifo.qsf

VERILOG HDL 实际工控项目源码

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		myfifo_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:39:49  SEPTEMBER 01, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION "4.1 SP2"
set_global_assignment -name BDF_FILE myfifo.bdf
set_global_assignment -name VERILOG_FILE mydram.v
set_global_assignment -name VERILOG_FILE wram.v
set_global_assignment -name VERILOG_FILE watchdog.v
set_global_assignment -name VERILOG_FILE ad_collect.v
set_global_assignment -name VERILOG_FILE addr_code.v
set_global_assignment -name VECTOR_WAVEFORM_FILE myfifo.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_55 -to g_clk
set_location_assignment PIN_81 -to d\[0\]
set_location_assignment PIN_82 -to d\[1\]
set_location_assignment PIN_83 -to d\[2\]
set_location_assignment PIN_86 -to d\[3\]
set_location_assignment PIN_87 -to d\[4\]
set_location_assignment PIN_88 -to d\[5\]
set_location_assignment PIN_89 -to d\[6\]
set_location_assignment PIN_90 -to d\[7\]
set_location_assignment PIN_91 -to d\[8\]
set_location_assignment PIN_92 -to d\[9\]
set_location_assignment PIN_95 -to d\[10\]
set_location_assignment PIN_96 -to d\[11\]
set_location_assignment PIN_97 -to d\[12\]
set_location_assignment PIN_98 -to d\[13\]
set_location_assignment PIN_99 -to d\[14\]
set_location_assignment PIN_100 -to d\[15\]
set_location_assignment PIN_124 -to ad_busy
set_location_assignment PIN_116 -to ad_conv
set_location_assignment PIN_114 -to ad_cs
set_location_assignment PIN_126 -to ad_eoc
set_location_assignment PIN_113 -to ad_rd
set_location_assignment PIN_111 -to ad_sl\[0\]
set_location_assignment PIN_110 -to ad_sl\[1\]
set_location_assignment PIN_109 -to ad_sl\[2\]
set_location_assignment PIN_102 -to ad_sl\[3\]
set_location_assignment PIN_101 -to ad_sel
set_location_assignment PIN_112 -to ad_wr
set_location_assignment PIN_80 -to rd_addr\[0\]
set_location_assignment PIN_79 -to rd_addr\[1\]
set_location_assignment PIN_78 -to rd_addr\[2\]
set_location_assignment PIN_73 -to rd_addr\[3\]
set_location_assignment PIN_72 -to rd_addr\[4\]
set_location_assignment PIN_70 -to rd_addr\[5\]
set_location_assignment PIN_69 -to rd_addr\[6\]
set_location_assignment PIN_67 -to rd_add\[12\]
set_location_assignment PIN_65 -to rd_add\[13\]
set_location_assignment PIN_64 -to rd_add\[14\]
set_location_assignment PIN_63 -to rd_add\[15\]
set_location_assignment PIN_62 -to page\[0\]
set_location_assignment PIN_60 -to page\[1\]
set_location_assignment PIN_59 -to page\[2\]
set_location_assignment PIN_51 -to page\[3\]
set_location_assignment PIN_49 -to rd_clk
set_location_assignment PIN_117 -to ad_db\[0\]
set_location_assignment PIN_118 -to ad_db\[1\]
set_location_assignment PIN_119 -to ad_db\[2\]
set_location_assignment PIN_120 -to ad_db\[3\]
set_location_assignment PIN_121 -to ad_db\[4\]
set_location_assignment PIN_130 -to ad_db\[5\]
set_location_assignment PIN_131 -to ad_db\[6\]
set_location_assignment PIN_132 -to ad_db\[7\]
set_location_assignment PIN_133 -to ad_db\[8\]
set_location_assignment PIN_135 -to ad_db\[9\]
set_location_assignment PIN_136 -to ad_db\[10\]
set_location_assignment PIN_137 -to ad_db\[11\]
set_location_assignment PIN_138 -to ad_db\[12\]
set_location_assignment PIN_8 -to mcu_a\[14\]
set_location_assignment PIN_9 -to mcu_a\[12\]
set_location_assignment PIN_10 -to mcu_a\[15\]
set_location_assignment PIN_12 -to mcu_a\[13\]
set_location_assignment PIN_13 -to mcu_rd
set_location_assignment PIN_17 -to mcu_wr
set_location_assignment PIN_18 -to can_cs
set_location_assignment PIN_19 -to addr_cs
set_location_assignment PIN_47 -to strb
set_location_assignment PIN_42 -to full_int
set_location_assignment PIN_37 -to dsp_sram_ce
set_location_assignment PIN_38 -to dsp_sram_oe
set_location_assignment PIN_36 -to dsp_sram_we
set_location_assignment PIN_46 -to dsp_flash_ce
set_location_assignment PIN_44 -to dsp_flash_oe
set_location_assignment PIN_48 -to dsp_flash_we
set_location_assignment PIN_29 -to bus1_ce
set_location_assignment PIN_30 -to bus1_dir
set_location_assignment PIN_32 -to bus2_dir
set_location_assignment PIN_31 -to bus2_ce
set_location_assignment PIN_41 -to dsp_tck0
set_location_assignment PIN_39 -to dsp_tck1
set_location_assignment PIN_27 -to dsp_run
set_location_assignment PIN_140 -to ad_db\[13\]
set_location_assignment PIN_33 -to dsp_rdy
set_location_assignment PIN_43 -to dsp_rst
set_location_assignment PIN_21 -to dsp_dram_ce
set_location_assignment PIN_26 -to dsp_dram_oe
set_location_assignment PIN_22 -to dsp_dram_rw
set_location_assignment PIN_20 -to mcu_dram_ce
set_location_assignment PIN_23 -to dram_busy
set_location_assignment PIN_28 -to dog_en
set_location_assignment PIN_68 -to rd_addr\[7\]
set_location_assignment PIN_142 -to dir_4052

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY FLEX10K
set_global_assignment -name TOP_LEVEL_ENTITY myfifo

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPF10K20TC144-4"
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD LVTTL/LVCMOS

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog HDL output from Quartus II)"

# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE OFF
set_global_assignment -name USE_CHECKSUM_AS_USERCODE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC1441
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE OFF
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE OFF
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE OFF
set_global_assignment -name GENERATE_TTF_FILE OFF
set_global_assignment -name GENERATE_RBF_FILE OFF
set_global_assignment -name GENERATE_HEX_FILE OFF

# Programmer Assignments
# ======================
set_global_assignment -name GENERATE_JAM_FILE ON
set_global_assignment -name GENERATE_JBC_FILE OFF
set_global_assignment -name GENERATE_CONFIG_SVF_FILE OFF
set_global_assignment -name GENERATE_CONFIG_JAM_FILE ON
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED OFF

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------