myfifo.map.summary

来自「VERILOG HDL 实际工控项目源码」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Thu Oct 14 17:17:01 2004
Quartus II Version : 4.1 Build 208 09/10/2004 SP 2 SJ Full Version
Revision Name : myfifo
Top-level Entity Name : myfifo
Family : FLEX10K
Device : EPF10K20TC144-4
Timing Models : Production
Total logic elements : 483
Total pins : 91
Total memory bits : 0