myfifo.vo

VERILOG HDL 实际工控项目源码

	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[2] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[3] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[3] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[3]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[3]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[3]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[3]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[3]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[3]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC5_F13
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[2]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[2]  = \inst1|delay[2]  $ \inst1|add_rtl_2|adder|result_node|cout[1] 
// \inst1|add_rtl_2|adder|result_node|cout[2]  = CARRY(\inst1|delay[2]  & \inst1|add_rtl_2|adder|result_node|cout[1] )

	.dataa(vcc),
	.datab(\inst1|delay[2] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[1] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[2] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[2] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[2]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[2]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[2]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[2]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[2]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[2]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC1_F3
flex10ke_lcell \inst1|reduce_or~11_I (
// Equation(s):
// \inst1|reduce_or~11  = \inst1|step~67  # \inst1|step~66  # \inst1|step~62  # !\inst1|reduce_or~54 

	.dataa(\inst1|reduce_or~54 ),
	.datab(\inst1|step~67 ),
	.datac(\inst1|step~66 ),
	.datad(\inst1|step~62 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|reduce_or~11 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|reduce_or~11_I .operation_mode = "normal";
defparam \inst1|reduce_or~11_I .packed_mode = "false";
defparam \inst1|reduce_or~11_I .lut_mask = "FFFD";
defparam \inst1|reduce_or~11_I .clock_enable_mode = "false";
defparam \inst1|reduce_or~11_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC7_B3
flex10ke_lcell \inst2|reduce_nor~99_I (
// Equation(s):
// \inst2|reduce_nor~99_cascout  = !\inst2|rdy_reg[6]  & !\inst2|rdy_reg[9]  & \inst2|rdy_reg[7]  & \inst2|rdy_reg[8] 

	.dataa(\inst2|rdy_reg[6] ),
	.datab(\inst2|rdy_reg[9] ),
	.datac(\inst2|rdy_reg[7] ),
	.datad(\inst2|rdy_reg[8] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(),
	.cout(),
	.cascout(\inst2|reduce_nor~99_cascout ));
// synopsys translate_off
defparam \inst2|reduce_nor~99_I .operation_mode = "normal";
defparam \inst2|reduce_nor~99_I .packed_mode = "false";
defparam \inst2|reduce_nor~99_I .lut_mask = "1000";
defparam \inst2|reduce_nor~99_I .clock_enable_mode = "false";
defparam \inst2|reduce_nor~99_I .output_mode = "none";
// synopsys translate_on

// atom is at LC8_B3
flex10ke_lcell \inst2|reduce_nor~101_I (
// Equation(s):
// \inst2|reduce_nor~101  = (!\inst2|rdy_reg[11]  & !\inst2|rdy_reg[12]  & \inst2|rdy_reg[10]  & \inst2|rdy_reg[13] ) & CASCADE(\inst2|reduce_nor~99_cascout )

	.dataa(\inst2|rdy_reg[11] ),
	.datab(\inst2|rdy_reg[12] ),
	.datac(\inst2|rdy_reg[10] ),
	.datad(\inst2|rdy_reg[13] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(\inst2|reduce_nor~99_cascout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|reduce_nor~101 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|reduce_nor~101_I .operation_mode = "normal";
defparam \inst2|reduce_nor~101_I .packed_mode = "false";
defparam \inst2|reduce_nor~101_I .lut_mask = "1000";
defparam \inst2|reduce_nor~101_I .clock_enable_mode = "false";
defparam \inst2|reduce_nor~101_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC6_F15
flex10ke_lcell \inst1|add_rtl_2|adder|unreg_res_node[11]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|unreg_res_node[11]  = \inst1|add_rtl_2|adder|result_node|cout[10]  $ \inst1|delay[11] 

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\inst1|delay[11] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[10] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|unreg_res_node[11] ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|unreg_res_node[11]~I .operation_mode = "normal";
defparam \inst1|add_rtl_2|adder|unreg_res_node[11]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|unreg_res_node[11]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|unreg_res_node[11]~I .lut_mask = "0FF0";
defparam \inst1|add_rtl_2|adder|unreg_res_node[11]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|unreg_res_node[11]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC4_F13
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[1]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[1]  = \inst1|delay[1]  $ \inst1|add_rtl_2|adder|result_node|cout[0] 
// \inst1|add_rtl_2|adder|result_node|cout[1]  = CARRY(\inst1|delay[1]  & \inst1|add_rtl_2|adder|result_node|cout[0] )

	.dataa(vcc),
	.datab(\inst1|delay[1] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[0] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[1] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[1] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[1]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[1]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[1]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[1]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[1]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[1]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC5_B17
flex10ke_lcell \inst2|coll_mem[4][13]~I (
// Equation(s):
// \inst2|coll_mem[4][13]  = DFFEA(!\ad_db[13]~dataout , GLOBAL(\g_clk~dataout ), , , \inst2|coll_mem[4][13]~42 , , )

	.dataa(\inst2|coll_mem[4][13]~42 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\ad_db[13]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|coll_mem[4][13] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|coll_mem[4][13]~I .operation_mode = "normal";
defparam \inst2|coll_mem[4][13]~I .packed_mode = "false";
defparam \inst2|coll_mem[4][13]~I .lut_mask = "00FF";
defparam \inst2|coll_mem[4][13]~I .clock_enable_mode = "true";
defparam \inst2|coll_mem[4][13]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC7_B17
flex10ke_lcell \inst2|coll_mem[7][13]~I (
// Equation(s):
// \inst2|coll_mem[7][13]  = DFFEA(!\ad_db[13]~dataout , GLOBAL(\g_clk~dataout ), , , \inst2|coll_mem[7][13]~0 , , )

	.dataa(\inst2|coll_mem[7][13]~0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\ad_db[13]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|coll_mem[7][13] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|coll_mem[7][13]~I .operation_mode = "normal";
defparam \inst2|coll_mem[7][13]~I .packed_mode = "false";
defparam \inst2|coll_mem[7][13]~I .lut_mask = "00FF";
defparam \inst2|coll_mem[7][13]~I .clock_enable_mode = "true";
defparam \inst2|coll_mem[7][13]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC5_B23
flex10ke_lcell \inst2|coll_mem[0][13]~I (
// Equation(s):
// \inst2|coll_mem[0][13]  = DFFEA(!\ad_db[13]~dataout , GLOBAL(\g_clk~dataout ), , , \inst2|coll_mem[0][13]~98 , , )

	.dataa(\inst2|coll_mem[0][13]~98 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\ad_db[13]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|coll_mem[0][13] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|coll_mem[0][13]~I .operation_mode = "normal";
defparam \inst2|coll_mem[0][13]~I .packed_mode = "false";
defparam \inst2|coll_mem[0][13]~I .lut_mask = "00FF";
defparam \inst2|coll_mem[0][13]~I .clock_enable_mode = "true";
defparam \inst2|coll_mem[0][13]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC1_B17
flex10ke_lcell \inst2|coll_mem[3][13]~I (
// Equation(s):
// \inst2|coll_mem[3][13]  = DFFEA(!\ad_db[13]~dataout , GLOBAL(\g_clk~dataout ), , , \inst2|coll_mem[3][13]~56 , , )

	.dataa(\inst2|coll_mem[3][13]~56 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\ad_db[13]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|coll_mem[3][13] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|coll_mem[3][13]~I .operation_mode = "normal";
defparam \inst2|coll_mem[3][13]~I .packed_mode = "false";
defparam \inst2|coll_mem[3][13]~I .lut_mask = "00FF";
defparam \inst2|coll_mem[3][13]~I .clock_enable_mode = "true";
defparam \inst2|coll_mem[3][13]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC5_B22
flex10ke_lcell \inst2|coll_mem[4][12]~I (
// Equation(s):
// \inst2|coll_mem[4][12]  = DFFEA(\ad_db[12]~dataout , GLOBAL(\g_clk~dataout ), , , \inst2|coll_mem[4][13]~42 , , )

	.dataa(\inst2|coll_mem[4][13]~42 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\ad_db[12]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|coll_mem[4][12] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|coll_mem[4][12]~I .operation_mode = "normal";
defparam \inst2|coll_mem[4][12]~I .packed_mode = "false";
defparam \inst2|coll_mem[4][12]~I .lut_mask = "FF00";
defparam \inst2|coll_mem[4][12]~I .clock_enable_mode = "true";
defparam \inst2|coll_mem[4][12]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC7_B22
flex10ke_lcell \inst2|coll_mem[7][12]~I (
// Equation(s):
// \inst2|coll_mem[7][12]  = DFFEA(\ad_db[12]~dataout , GLOBAL(\g_clk~dataout ), , , \inst2|coll_mem[7][13]~0 , , )

	.dataa(\inst2|coll_mem[7][13]~0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\ad_db[12]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|coll_mem[7][12] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|coll_mem[7][12]~I .operation_mode = "normal";
defparam \inst2|coll_mem[7][12]~I .packed_mode = "false";
defparam \inst2|coll_mem[7][12]~I .lut_mask = "FF00";
defparam \inst2|coll_mem[7][12]~I .clock_enable_mode = "true";
defparam \inst2|coll_mem[7][12]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC8_B23
flex10ke_lcell \inst2|coll_mem[0][12]~I (
// Equation(s):
// \inst2|coll_mem[0][12]  = DFFEA(\ad_db[12]~dataout , GLOBAL(\g_clk~dataout ), , , \inst2|coll_mem[0][13]~98 , , )

	.dataa(\inst2|coll_mem[0][13]~98 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\ad_db[12]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|coll_mem[0][12] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|coll_mem[0][12]~I .operation_mode = "normal";
defparam \inst2|coll_mem[0][12]~I .packed_mode = "false";
defparam \inst2|coll_mem[0][12]~I .lut_mask = "FF00";
defparam \inst2|coll_mem[0][12]~I .clock_enable_mode = "true";
defparam \inst2|coll_mem[0][12]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC1_B22
flex10ke_lcell \inst2|coll_mem[3][12]~I (
// Equation(s):
// \inst2|coll_mem[3][12]  = DFFE