myfifo.vo

VERILOG HDL 实际工控项目源码

defparam \inst1|LessThan~374_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC1_F18
flex10ke_lcell \inst1|LessThan~375_I (
// Equation(s):
// \inst1|LessThan~375  = \inst1|LessThan~373  # \inst1|delay[7]  # \inst1|LessThan~374  & \inst1|delay[5] 

	.dataa(\inst1|LessThan~374 ),
	.datab(\inst1|delay[5] ),
	.datac(\inst1|LessThan~373 ),
	.datad(\inst1|delay[7] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|LessThan~375 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|LessThan~375_I .operation_mode = "normal";
defparam \inst1|LessThan~375_I .packed_mode = "false";
defparam \inst1|LessThan~375_I .lut_mask = "FFF8";
defparam \inst1|LessThan~375_I .clock_enable_mode = "false";
defparam \inst1|LessThan~375_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC8_F21
flex10ke_lcell \inst1|change_end~10_I (
// Equation(s):
// \inst1|change_end~10  = \inst1|counter[0]  & \inst1|counter[1] 

	.dataa(vcc),
	.datab(vcc),
	.datac(\inst1|counter[0] ),
	.datad(\inst1|counter[1] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|change_end~10 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|change_end~10_I .operation_mode = "normal";
defparam \inst1|change_end~10_I .packed_mode = "false";
defparam \inst1|change_end~10_I .lut_mask = "F000";
defparam \inst1|change_end~10_I .clock_enable_mode = "false";
defparam \inst1|change_end~10_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC7_F16
flex10ke_lcell \inst1|change_end~I (
// Equation(s):
// \inst1|change_end  = DFFEA(!\inst1|change_end , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , \inst1|change_end~11 , , )

	.dataa(\inst1|change_end~11 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\inst1|change_end ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|change_end ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|change_end~I .operation_mode = "normal";
defparam \inst1|change_end~I .packed_mode = "false";
defparam \inst1|change_end~I .lut_mask = "00FF";
defparam \inst1|change_end~I .clock_enable_mode = "true";
defparam \inst1|change_end~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC5_F21
flex10ke_lcell \inst1|change_end~11_I (
// Equation(s):
// \inst1|change_end~11  = \inst1|counter[0]  & \inst1|counter[1]  & \inst1|step~61 

	.dataa(vcc),
	.datab(\inst1|counter[0] ),
	.datac(\inst1|counter[1] ),
	.datad(\inst1|step~61 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|change_end~11 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|change_end~11_I .operation_mode = "normal";
defparam \inst1|change_end~11_I .packed_mode = "false";
defparam \inst1|change_end~11_I .lut_mask = "C000";
defparam \inst1|change_end~11_I .clock_enable_mode = "false";
defparam \inst1|change_end~11_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC2_E16
flex10ke_lcell \inst|watch_reg~52_I (
// Equation(s):
// \inst|watch_reg~52  = !\inst|watch_reg[25]  & \inst|LessThan~403  & (\inst|dog_reg[0]  $ !\inst|dog_reg[1] )

	.dataa(\inst|watch_reg[25] ),
	.datab(\inst|dog_reg[0] ),
	.datac(\inst|dog_reg[1] ),
	.datad(\inst|LessThan~403 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst|watch_reg~52 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst|watch_reg~52_I .operation_mode = "normal";
defparam \inst|watch_reg~52_I .packed_mode = "false";
defparam \inst|watch_reg~52_I .lut_mask = "4100";
defparam \inst|watch_reg~52_I .clock_enable_mode = "false";
defparam \inst|watch_reg~52_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC1_F14
flex10ke_lcell \inst1|reduce_or~9_I (
// Equation(s):
// \inst1|reduce_or~9  = \inst1|step~61  # \inst1|step~62  # \inst1|step~67  # !\inst1|reduce_or~54 

	.dataa(\inst1|reduce_or~54 ),
	.datab(\inst1|step~61 ),
	.datac(\inst1|step~62 ),
	.datad(\inst1|step~67 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|reduce_or~9 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|reduce_or~9_I .operation_mode = "normal";
defparam \inst1|reduce_or~9_I .packed_mode = "false";
defparam \inst1|reduce_or~9_I .lut_mask = "FFFD";
defparam \inst1|reduce_or~9_I .clock_enable_mode = "false";
defparam \inst1|reduce_or~9_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC2_F15
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[7]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[7]  = \inst1|delay[7]  $ \inst1|add_rtl_2|adder|result_node|cout[6] 
// \inst1|add_rtl_2|adder|result_node|cout[7]  = CARRY(\inst1|delay[7]  & \inst1|add_rtl_2|adder|result_node|cout[6] )

	.dataa(vcc),
	.datab(\inst1|delay[7] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[6] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[7] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[7] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[7]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[7]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[7]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[7]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[7]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[7]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC5_F15
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[10]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[10]  = \inst1|delay[10]  $ \inst1|add_rtl_2|adder|result_node|cout[9] 
// \inst1|add_rtl_2|adder|result_node|cout[10]  = CARRY(\inst1|delay[10]  & \inst1|add_rtl_2|adder|result_node|cout[9] )

	.dataa(vcc),
	.datab(\inst1|delay[10] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[9] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[10] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[10] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[10]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[10]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[10]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[10]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[10]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[10]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC4_F15
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[9]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[9]  = \inst1|delay[9]  $ \inst1|add_rtl_2|adder|result_node|cout[8] 
// \inst1|add_rtl_2|adder|result_node|cout[9]  = CARRY(\inst1|delay[9]  & \inst1|add_rtl_2|adder|result_node|cout[8] )

	.dataa(vcc),
	.datab(\inst1|delay[9] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[8] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[9] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[9] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[9]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[9]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[9]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[9]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[9]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[9]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC3_F15
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[8]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[8]  = \inst1|delay[8]  $ \inst1|add_rtl_2|adder|result_node|cout[7] 
// \inst1|add_rtl_2|adder|result_node|cout[8]  = CARRY(\inst1|delay[8]  & \inst1|add_rtl_2|adder|result_node|cout[7] )

	.dataa(vcc),
	.datab(\inst1|delay[8] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[7] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[8] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[8] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[8]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[8]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[8]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[8]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[8]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[8]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC8_F13
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[5]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[5]  = \inst1|delay[5]  $ \inst1|add_rtl_2|adder|result_node|cout[4] 
// \inst1|add_rtl_2|adder|result_node|cout[5]  = CARRY(\inst1|delay[5]  & \inst1|add_rtl_2|adder|result_node|cout[4] )

	.dataa(vcc),
	.datab(\inst1|delay[5] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[4] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[5] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[5] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[5]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[5]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[5]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[5]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[5]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[5]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC1_F15
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[6]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[6]  = \inst1|delay[6]  $ \inst1|add_rtl_2|adder|result_node|cout[5] 
// \inst1|add_rtl_2|adder|result_node|cout[6]  = CARRY(\inst1|delay[6]  & \inst1|add_rtl_2|adder|result_node|cout[5] )

	.dataa(vcc),
	.datab(\inst1|delay[6] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[5] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[6] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[6] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[6]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[6]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[6]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[6]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[6]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[6]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC7_F13
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[4]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[4]  = \inst1|delay[4]  $ \inst1|add_rtl_2|adder|result_node|cout[3] 
// \inst1|add_rtl_2|adder|result_node|cout[4]  = CARRY(\inst1|delay[4]  & \inst1|add_rtl_2|adder|result_node|cout[3] )

	.dataa(vcc),
	.datab(\inst1|delay[4] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst1|add_rtl_2|adder|result_node|cout[3] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add_rtl_2|adder|result_node|cs_buffer[4] ),
	.regout(),
	.cout(\inst1|add_rtl_2|adder|result_node|cout[4] ),
	.cascout());
// synopsys translate_off
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[4]~I .operation_mode = "arithmetic";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[4]~I .cin_used = "true";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[4]~I .packed_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[4]~I .lut_mask = "3CC0";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[4]~I .clock_enable_mode = "false";
defparam \inst1|add_rtl_2|adder|result_node|cs_buffer[4]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC6_F13
flex10ke_lcell \inst1|add_rtl_2|adder|result_node|cs_buffer[3]~I (
// Equation(s):
// \inst1|add_rtl_2|adder|result_node|cs_buffer[3]  = \inst1|delay[3]  $ \inst1|add_rtl_2|adder|result_node|cout[2] 
// \inst1|add_rtl_2|adder|result_node|cout[3]  = CARRY(\inst1|delay[3]  & \inst1|add_rtl_2|adder|result_node|cout[2] )

	.dataa(vcc),
	.datab(\inst1|delay[3] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),