myfifo.vo

VERILOG HDL 实际工控项目源码

defparam \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6] .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC2_E5
flex10ke_lcell \inst2|reduce_nor~94_I (
// Equation(s):
// \inst2|reduce_nor~94  = \inst2|rdy_reg[3]  # \inst2|rdy_reg[4]  # !\inst2|rdy_reg[5]  # !\inst2|rdy_reg[2] 

	.dataa(\inst2|rdy_reg[2] ),
	.datab(\inst2|rdy_reg[5] ),
	.datac(\inst2|rdy_reg[3] ),
	.datad(\inst2|rdy_reg[4] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|reduce_nor~94 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|reduce_nor~94_I .operation_mode = "normal";
defparam \inst2|reduce_nor~94_I .packed_mode = "false";
defparam \inst2|reduce_nor~94_I .lut_mask = "FFF7";
defparam \inst2|reduce_nor~94_I .clock_enable_mode = "false";
defparam \inst2|reduce_nor~94_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC5_D4
flex10ke_lcell \inst2|reduce_nor~96_I (
// Equation(s):
// \inst2|reduce_nor~96  = \inst2|rdy_reg[0]  & \inst2|reduce_nor~101  & !\inst2|rdy_reg[1]  & !\inst2|reduce_nor~94 

	.dataa(\inst2|rdy_reg[0] ),
	.datab(\inst2|reduce_nor~101 ),
	.datac(\inst2|rdy_reg[1] ),
	.datad(\inst2|reduce_nor~94 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst2|reduce_nor~96 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst2|reduce_nor~96_I .operation_mode = "normal";
defparam \inst2|reduce_nor~96_I .packed_mode = "false";
defparam \inst2|reduce_nor~96_I .lut_mask = "0008";
defparam \inst2|reduce_nor~96_I .clock_enable_mode = "false";
defparam \inst2|reduce_nor~96_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC6_F16
flex10ke_lcell \inst1|delay[7]~I (
// Equation(s):
// \inst1|delay[7]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[7]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[7] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[7]  & \inst1|reduce_or~9  & \inst1|delay[7] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[7] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[7] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[7] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[7]~I .operation_mode = "normal";
defparam \inst1|delay[7]~I .packed_mode = "false";
defparam \inst1|delay[7]~I .lut_mask = "EAC0";
defparam \inst1|delay[7]~I .clock_enable_mode = "false";
defparam \inst1|delay[7]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC7_F18
flex10ke_lcell \inst1|delay[11]~I (
// Equation(s):
// \inst1|delay[11]  = DFFEA(\inst1|add_rtl_2|adder|unreg_res_node[11]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[11] ) # !\inst1|add_rtl_2|adder|unreg_res_node[11]  & \inst1|reduce_or~9  & \inst1|delay[11] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|unreg_res_node[11] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[11] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[11] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[11]~I .operation_mode = "normal";
defparam \inst1|delay[11]~I .packed_mode = "false";
defparam \inst1|delay[11]~I .lut_mask = "EAC0";
defparam \inst1|delay[11]~I .clock_enable_mode = "false";
defparam \inst1|delay[11]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC6_F18
flex10ke_lcell \inst1|delay[10]~I (
// Equation(s):
// \inst1|delay[10]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[10]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[10] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[10]  & \inst1|reduce_or~9  & \inst1|delay[10] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[10] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[10] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[10] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[10]~I .operation_mode = "normal";
defparam \inst1|delay[10]~I .packed_mode = "false";
defparam \inst1|delay[10]~I .lut_mask = "EAC0";
defparam \inst1|delay[10]~I .clock_enable_mode = "false";
defparam \inst1|delay[10]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC3_F18
flex10ke_lcell \inst1|delay[9]~I (
// Equation(s):
// \inst1|delay[9]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[9]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[9] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[9]  & \inst1|reduce_or~9  & \inst1|delay[9] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[9] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[9] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[9] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[9]~I .operation_mode = "normal";
defparam \inst1|delay[9]~I .packed_mode = "false";
defparam \inst1|delay[9]~I .lut_mask = "EAC0";
defparam \inst1|delay[9]~I .clock_enable_mode = "false";
defparam \inst1|delay[9]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC1_F16
flex10ke_lcell \inst1|delay[8]~I (
// Equation(s):
// \inst1|delay[8]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[8]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[8] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[8]  & \inst1|reduce_or~9  & \inst1|delay[8] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[8] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[8] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[8] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[8]~I .operation_mode = "normal";
defparam \inst1|delay[8]~I .packed_mode = "false";
defparam \inst1|delay[8]~I .lut_mask = "EAC0";
defparam \inst1|delay[8]~I .clock_enable_mode = "false";
defparam \inst1|delay[8]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC2_F18
flex10ke_lcell \inst1|LessThan~373_I (
// Equation(s):
// \inst1|LessThan~373  = \inst1|delay[8]  # \inst1|delay[9]  # \inst1|delay[10]  # \inst1|delay[11] 

	.dataa(\inst1|delay[8] ),
	.datab(\inst1|delay[9] ),
	.datac(\inst1|delay[10] ),
	.datad(\inst1|delay[11] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|LessThan~373 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|LessThan~373_I .operation_mode = "normal";
defparam \inst1|LessThan~373_I .packed_mode = "false";
defparam \inst1|LessThan~373_I .lut_mask = "FFFE";
defparam \inst1|LessThan~373_I .clock_enable_mode = "false";
defparam \inst1|LessThan~373_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC4_F18
flex10ke_lcell \inst1|delay[5]~I (
// Equation(s):
// \inst1|delay[5]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[5]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[5] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[5]  & \inst1|reduce_or~9  & \inst1|delay[5] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[5] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[5] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[5] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[5]~I .operation_mode = "normal";
defparam \inst1|delay[5]~I .packed_mode = "false";
defparam \inst1|delay[5]~I .lut_mask = "EAC0";
defparam \inst1|delay[5]~I .clock_enable_mode = "false";
defparam \inst1|delay[5]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC8_F14
flex10ke_lcell \inst1|delay[6]~I (
// Equation(s):
// \inst1|delay[6]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[6]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[6] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[6]  & \inst1|reduce_or~9  & \inst1|delay[6] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[6] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[6] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[6] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[6]~I .operation_mode = "normal";
defparam \inst1|delay[6]~I .packed_mode = "false";
defparam \inst1|delay[6]~I .lut_mask = "EAC0";
defparam \inst1|delay[6]~I .clock_enable_mode = "false";
defparam \inst1|delay[6]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC7_F14
flex10ke_lcell \inst1|delay[4]~I (
// Equation(s):
// \inst1|delay[4]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[4]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[4] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[4]  & \inst1|reduce_or~9  & \inst1|delay[4] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[4] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[4] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[4] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[4]~I .operation_mode = "normal";
defparam \inst1|delay[4]~I .packed_mode = "false";
defparam \inst1|delay[4]~I .lut_mask = "EAC0";
defparam \inst1|delay[4]~I .clock_enable_mode = "false";
defparam \inst1|delay[4]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC5_F14
flex10ke_lcell \inst1|delay[3]~I (
// Equation(s):
// \inst1|delay[3]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[3]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[3] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[3]  & \inst1|reduce_or~9  & \inst1|delay[3] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[3] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[3] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[3] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[3]~I .operation_mode = "normal";
defparam \inst1|delay[3]~I .packed_mode = "false";
defparam \inst1|delay[3]~I .lut_mask = "EAC0";
defparam \inst1|delay[3]~I .clock_enable_mode = "false";
defparam \inst1|delay[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC4_F14
flex10ke_lcell \inst1|delay[2]~I (
// Equation(s):
// \inst1|delay[2]  = DFFEA(\inst1|add_rtl_2|adder|result_node|cs_buffer[2]  & (\inst1|Select~2336  # \inst1|reduce_or~9  & \inst1|delay[2] ) # !\inst1|add_rtl_2|adder|result_node|cs_buffer[2]  & \inst1|reduce_or~9  & \inst1|delay[2] , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )

	.dataa(\inst1|add_rtl_2|adder|result_node|cs_buffer[2] ),
	.datab(\inst1|reduce_or~9 ),
	.datac(\inst1|delay[2] ),
	.datad(\inst1|Select~2336 ),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|delay[2] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|delay[2]~I .operation_mode = "normal";
defparam \inst1|delay[2]~I .packed_mode = "false";
defparam \inst1|delay[2]~I .lut_mask = "EAC0";
defparam \inst1|delay[2]~I .clock_enable_mode = "false";
defparam \inst1|delay[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC2_F14
flex10ke_lcell \inst1|LessThan~374_I (
// Equation(s):
// \inst1|LessThan~374  = \inst1|delay[6]  & (\inst1|delay[2]  # \inst1|delay[3]  # \inst1|delay[4] )

	.dataa(\inst1|delay[2] ),
	.datab(\inst1|delay[3] ),
	.datac(\inst1|delay[4] ),
	.datad(\inst1|delay[6] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|LessThan~374 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst1|LessThan~374_I .operation_mode = "normal";
defparam \inst1|LessThan~374_I .packed_mode = "false";
defparam \inst1|LessThan~374_I .lut_mask = "FE00";
defparam \inst1|LessThan~374_I .clock_enable_mode = "false";