myfifo.vo

VERILOG HDL 实际工控项目源码

wire \inst|watch_reg[21] ;
wire \inst|add_rtl_1|adder|result_node|cout[21] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[22] ;
wire \inst|Select~2640 ;
wire \inst|watch_reg[22] ;
wire \inst|add_rtl_1|adder|result_node|cout[22] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[23] ;
wire \inst|Select~2636 ;
wire \inst|watch_reg[23] ;
wire \inst|LessThan~401 ;
wire \inst|LessThan~402 ;
wire \inst|LessThan~398 ;
wire \inst|LessThan~397 ;
wire \inst|LessThan~399 ;
wire \inst|LessThan~400 ;
wire \inst|LessThan~403 ;
wire \inst|step~19 ;
wire \inst|step~21 ;
wire \inst|add_rtl_1|adder|result_node|cout[23] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[24] ;
wire \inst|Select~2645 ;
wire \inst|watch_reg[24] ;
wire \inst|add_rtl_1|adder|result_node|cout[24] ;
wire \inst|add_rtl_1|adder|unreg_res_node[25] ;
wire \inst|Select~2646 ;
wire \inst|watch_reg[25] ;
wire \dog_en~dataout ;
wire \strb~dataout ;
wire \rd_add[12]~dataout ;
wire \rd_add[15]~dataout ;
wire \inst5|dsp_dram_ce~24 ;
wire \rd_add[13]~dataout ;
wire \rd_add[14]~dataout ;
wire \inst|feed_dog ;
wire \inst|dog_clk ;
wire \inst|dog_reg[0] ;
wire \inst|dog_reg[1] ;
wire \inst|Select~2625 ;
wire \inst|Select~50 ;
wire \inst|rst ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[0]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[1]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[2]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[3]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[4]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[5] ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[3] ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[4] ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[3]~104 ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[5]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[7]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[8] ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[8]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[9] ;
wire \inst1|int_reg_rtl_0|wysi_counter|counter_cell[9]~COUT ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[10] ;
wire \inst1|int_reg~114 ;
wire \inst1|int_reg~34 ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[7] ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[1] ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[2] ;
wire \inst1|LessThan~371 ;
wire \inst1|LessThan~372 ;
wire \inst1|full_int~107 ;
wire \inst1|full_int~106 ;
wire \inst1|full_int ;
wire \ad_eoc~dataout ;
wire \inst1|eoc_reg[0] ;
wire \inst1|eoc_reg[1] ;
wire \inst1|step~64 ;
wire \inst1|step~63 ;
wire \inst1|step~62 ;
wire \inst1|step~61 ;
wire \inst1|step~66 ;
wire \inst1|Select~2336 ;
wire \inst1|step~65 ;
wire \inst1|Select~2340 ;
wire \inst1|counter[0] ;
wire \inst1|Select~126 ;
wire \inst1|counter[1] ;
wire \inst1|step~59 ;
wire \inst1|collect_reg[0] ;
wire \inst1|collect_reg[1] ;
wire \inst1|Select~2338 ;
wire \inst1|step~60 ;
wire \inst1|Select~2343_cascout ;
wire \inst1|Select~2345 ;
wire \inst1|step~67 ;
wire \inst1|reduce_or~54 ;
wire \inst1|reduce_or~55 ;
wire \inst1|Select~2329 ;
wire \inst1|ad_cs ;
wire \inst1|Select~2331 ;
wire \inst1|Select~2332 ;
wire \inst1|ad_rd ;
wire \inst1|Select~2334 ;
wire \inst1|ad_conv ;
wire \page[3]~dataout ;
wire \inst5|dsp_sram_ce ;
wire \rd_clk~dataout ;
wire \inst5|dsp_flash_oe ;
wire \inst5|dsp_dram_rw ;
wire \page[1]~dataout ;
wire \inst5|dsp_flash_ce ;
wire \inst5|dsp_flash_oe~7 ;
wire \inst5|dsp_dram_rw~7 ;
wire \page[2]~dataout ;
wire \inst5|bus1_ce ;
wire \bus1_dir~0 ;
wire \mcu_a[12]~dataout ;
wire \mcu_a[14]~dataout ;
wire \mcu_a[13]~dataout ;
wire \mcu_a[15]~dataout ;
wire \inst5|mcu_dram_ce~6 ;
wire \mcu_wr~dataout ;
wire \mcu_rd~dataout ;
wire \inst5|can_cs ;
wire \inst5|mcu_dram_ce~7 ;
wire \inst5|addr_cs ;
wire \inst5|wr_led ;
wire \inst5|dsp_run ;
wire \dram_busy~dataout ;
wire \inst2|dsp_rdy_en ;
wire \inst2|dsp_rdy ;
wire \dsp_rst~0 ;
wire \inst5|dsp_dram_ce ;
wire \inst5|dsp_flash_oe~8 ;
wire \inst5|dsp_dram_rw~8 ;
wire \inst5|mcu_dram_ce ;
wire \inst2|rd_en~42 ;
wire \inst2|rd_en ;
wire \d[15]~30 ;
wire \inst2|rd_en~43 ;
wire \inst2|rdy_en ;
wire \inst2|rdy_reg[13] ;
wire \inst2|coll_mem[8][13] ;
wire \rd_addr[3]~dataout ;
wire \rd_addr[2]~dataout ;
wire \rd_addr[0]~dataout ;
wire \ad_db[13]~dataout ;
wire \inst2|coll_mem[1][13] ;
wire \rd_addr[1]~dataout ;
wire \inst2|Mux~292 ;
wire \inst2|coll_mem[2][13] ;
wire \inst2|Mux~293 ;
wire \inst2|coll_mem[6][13] ;
wire \inst2|Mux~294 ;
wire \inst2|coll_mem[5][13] ;
wire \inst2|Mux~295 ;
wire \inst2|Mux~616 ;
wire \inst2|Mux~617 ;
wire \inst2|d_out[13]~2394_cascout ;
wire \inst2|d_out[13]~2436_cascout ;
wire \inst2|d_out[13]~2422 ;
wire \inst2|rdy_reg[12] ;
wire \inst2|coll_mem[8][12] ;
wire \ad_db[12]~dataout ;
wire \inst2|coll_mem[1][12] ;
wire \inst2|Mux~296 ;
wire \inst2|coll_mem[2][12] ;
wire \inst2|Mux~297 ;
wire \inst2|coll_mem[6][12] ;
wire \inst2|Mux~298 ;
wire \inst2|coll_mem[5][12] ;
wire \inst2|Mux~299 ;
wire \inst2|Mux~618 ;
wire \inst2|Mux~619 ;
wire \inst2|d_out[12]~2396_cascout ;
wire \inst2|d_out[12]~2437_cascout ;
wire \inst2|d_out[12]~2423 ;
wire \inst2|rdy_reg[11] ;
wire \inst2|coll_mem[8][11] ;
wire \ad_db[11]~dataout ;
wire \inst2|coll_mem[1][11] ;
wire \inst2|Mux~300 ;
wire \inst2|coll_mem[2][11] ;
wire \inst2|Mux~301 ;
wire \inst2|coll_mem[6][11] ;
wire \inst2|Mux~302 ;
wire \inst2|coll_mem[5][11] ;
wire \inst2|Mux~303 ;
wire \inst2|Mux~620 ;
wire \inst2|Mux~621 ;
wire \inst2|d_out[11]~2398_cascout ;
wire \inst2|d_out[11]~2438_cascout ;
wire \inst2|d_out[11]~2424 ;
wire \inst2|rdy_reg[10] ;
wire \inst2|coll_mem[8][10] ;
wire \ad_db[10]~dataout ;
wire \inst2|coll_mem[1][10] ;
wire \inst2|Mux~304 ;
wire \inst2|coll_mem[2][10] ;
wire \inst2|Mux~305 ;
wire \inst2|coll_mem[6][10] ;
wire \inst2|Mux~306 ;
wire \inst2|coll_mem[5][10] ;
wire \inst2|Mux~307 ;
wire \inst2|Mux~622 ;
wire \inst2|Mux~623 ;
wire \inst2|d_out[10]~2400_cascout ;
wire \inst2|d_out[10]~2439_cascout ;
wire \inst2|d_out[10]~2425 ;
wire \inst2|rdy_reg[9] ;
wire \inst2|coll_mem[8][9] ;
wire \ad_db[9]~dataout ;
wire \inst2|coll_mem[1][9] ;
wire \inst2|Mux~308 ;
wire \inst2|coll_mem[2][9] ;
wire \inst2|Mux~309 ;
wire \inst2|coll_mem[6][9] ;
wire \inst2|Mux~310 ;
wire \inst2|coll_mem[5][9] ;
wire \inst2|Mux~311 ;
wire \inst2|Mux~624 ;
wire \inst2|Mux~625 ;
wire \inst2|d_out[9]~2402_cascout ;
wire \inst2|d_out[9]~2440_cascout ;
wire \inst2|d_out[9]~2426 ;
wire \inst2|rdy_reg[8] ;
wire \inst2|coll_mem[8][8] ;
wire \ad_db[8]~dataout ;
wire \inst2|coll_mem[1][8] ;
wire \inst2|Mux~312 ;
wire \inst2|coll_mem[2][8] ;
wire \inst2|Mux~313 ;
wire \inst2|coll_mem[6][8] ;
wire \inst2|Mux~314 ;
wire \inst2|coll_mem[5][8] ;
wire \inst2|Mux~315 ;
wire \inst2|Mux~626 ;
wire \inst2|Mux~627 ;
wire \inst2|d_out[8]~2404_cascout ;
wire \inst2|d_out[8]~2441_cascout ;
wire \inst2|d_out[8]~2427 ;
wire \inst2|rdy_reg[7] ;
wire \inst2|coll_mem[8][7] ;
wire \ad_db[7]~dataout ;
wire \inst2|coll_mem[1][7] ;
wire \inst2|Mux~316 ;
wire \inst2|coll_mem[2][7] ;
wire \inst2|Mux~317 ;
wire \inst2|coll_mem[6][7] ;
wire \inst2|Mux~318 ;
wire \inst2|coll_mem[5][7] ;
wire \inst2|Mux~319 ;
wire \inst2|Mux~628 ;
wire \inst2|Mux~629 ;
wire \inst2|d_out[7]~2406_cascout ;
wire \inst2|d_out[7]~2442_cascout ;
wire \inst2|d_out[7]~2428 ;
wire \inst2|rdy_reg[6] ;
wire \inst2|coll_mem[8][6] ;
wire \ad_db[6]~dataout ;
wire \inst2|coll_mem[1][6] ;
wire \inst2|Mux~320 ;
wire \inst2|coll_mem[2][6] ;
wire \inst2|Mux~321 ;
wire \inst2|coll_mem[6][6] ;
wire \inst2|Mux~322 ;
wire \inst2|coll_mem[5][6] ;
wire \inst2|Mux~323 ;
wire \inst2|Mux~630 ;
wire \inst2|Mux~631 ;
wire \inst2|d_out[6]~2408_cascout ;
wire \inst2|d_out[6]~2443_cascout ;
wire \inst2|d_out[6]~2429 ;
wire \inst2|rdy_reg[5] ;
wire \inst2|coll_mem[8][5] ;
wire \ad_db[5]~dataout ;
wire \inst2|coll_mem[1][5] ;
wire \inst2|Mux~324 ;
wire \inst2|coll_mem[2][5] ;
wire \inst2|Mux~325 ;
wire \inst2|coll_mem[6][5] ;
wire \inst2|Mux~326 ;
wire \inst2|coll_mem[5][5] ;
wire \inst2|Mux~327 ;
wire \inst2|Mux~632 ;
wire \inst2|Mux~633 ;
wire \inst2|d_out[5]~2410_cascout ;
wire \inst2|d_out[5]~2444_cascout ;
wire \inst2|d_out[5]~2430 ;
wire \inst2|rdy_reg[4] ;
wire \inst2|coll_mem[8][4] ;
wire \ad_db[4]~dataout ;
wire \inst2|coll_mem[1][4] ;
wire \inst2|Mux~328 ;
wire \inst2|coll_mem[2][4] ;
wire \inst2|Mux~329 ;
wire \inst2|coll_mem[6][4] ;
wire \inst2|Mux~330 ;
wire \inst2|coll_mem[5][4] ;
wire \inst2|Mux~331 ;
wire \inst2|Mux~634 ;
wire \inst2|Mux~635 ;
wire \inst2|d_out[4]~2412_cascout ;
wire \inst2|d_out[4]~2445_cascout ;
wire \inst2|d_out[4]~2431 ;
wire \inst2|rdy_reg[3] ;
wire \inst2|coll_mem[8][3] ;
wire \ad_db[3]~dataout ;
wire \inst2|coll_mem[1][3] ;
wire \inst2|Mux~332 ;
wire \inst2|coll_mem[2][3] ;
wire \inst2|Mux~333 ;
wire \inst2|coll_mem[6][3] ;
wire \inst2|Mux~334 ;
wire \inst2|coll_mem[5][3] ;
wire \inst2|Mux~335 ;
wire \inst2|Mux~636 ;
wire \inst2|Mux~637 ;
wire \inst2|d_out[3]~2414_cascout ;
wire \inst2|d_out[3]~2446_cascout ;
wire \inst2|d_out[3]~2432 ;
wire \inst2|rdy_reg[2] ;
wire \inst2|coll_mem[8][2] ;
wire \ad_db[2]~dataout ;
wire \inst2|coll_mem[1][2] ;
wire \inst2|Mux~336 ;
wire \inst2|coll_mem[2][2] ;
wire \inst2|Mux~337 ;
wire \inst2|coll_mem[6][2] ;
wire \inst2|Mux~338 ;
wire \inst2|coll_mem[5][2] ;
wire \inst2|Mux~339 ;
wire \inst2|Mux~638 ;
wire \inst2|Mux~639 ;
wire \inst2|d_out[2]~2416_cascout ;
wire \inst2|d_out[2]~2447_cascout ;
wire \inst2|d_out[2]~2433 ;
wire \inst2|rdy_reg[1] ;
wire \inst2|coll_mem[8][1] ;
wire \ad_db[1]~dataout ;
wire \inst2|coll_mem[1][1] ;
wire \inst2|Mux~340 ;
wire \inst2|coll_mem[2][1] ;
wire \inst2|Mux~341 ;
wire \inst2|coll_mem[6][1] ;
wire \inst2|Mux~342 ;
wire \inst2|coll_mem[5][1] ;
wire \inst2|Mux~343 ;
wire \inst2|Mux~640 ;
wire \inst2|Mux~641 ;
wire \inst2|d_out[1]~2418_cascout ;
wire \inst2|d_out[1]~2448_cascout ;
wire \inst2|d_out[1]~2434 ;
wire \inst2|rdy_reg[0] ;
wire \inst2|coll_mem[8][0] ;
wire \ad_db[0]~dataout ;
wire \inst2|coll_mem[1][0] ;
wire \inst2|Mux~344 ;
wire \inst2|coll_mem[2][0] ;
wire \inst2|Mux~345 ;
wire \inst2|coll_mem[6][0] ;
wire \inst2|Mux~346 ;
wire \inst2|coll_mem[5][0] ;
wire \inst2|Mux~347 ;
wire \inst2|Mux~642 ;
wire \inst2|Mux~643 ;
wire \inst2|d_out[0]~2420_cascout ;
wire \inst2|d_out[0]~2449_cascout ;
wire \inst2|d_out[0]~2435 ;


// atom is at LC2_C15
flex10ke_lcell \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6] (
// Equation(s):
// \inst1|int_reg_rtl_0|wysi_counter|q[6]  = DFFEA((\inst1|int_reg_rtl_0|wysi_counter|q[6]  $ \inst1|int_reg_rtl_0|wysi_counter|counter_cell[5]~COUT ) & \inst1|int_reg~34 , GLOBAL(\g_clk~dataout ), !GLOBAL(\inst|rst ), , , , )
// \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6]~COUT  = CARRY(\inst1|int_reg_rtl_0|wysi_counter|q[6]  & \inst1|int_reg_rtl_0|wysi_counter|counter_cell[5]~COUT )

	.dataa(vcc),
	.datab(\inst1|int_reg~34 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(\inst|rst ),
	.aload(gnd),
	.clk(\g_clk~dataout ),
	.cin(\inst1|int_reg_rtl_0|wysi_counter|counter_cell[5]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|int_reg_rtl_0|wysi_counter|q[6] ),
	.cout(\inst1|int_reg_rtl_0|wysi_counter|counter_cell[6]~COUT ),
	.cascout());
// synopsys translate_off
defparam \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6] .operation_mode = "clrb_cntr";
defparam \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6] .cin_used = "true";
defparam \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6] .packed_mode = "false";
defparam \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6] .lut_mask = "3CA0";
defparam \inst1|int_reg_rtl_0|wysi_counter|counter_cell[6] .clock_enable_mode = "false";