myfifo.vo

VERILOG HDL 实际工控项目源码

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version"

// DATE "10/14/2004 17:17:36"

// 
// Device: Altera EPF10K20TC144-4 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

`timescale 1 ps/ 1 ps

module 	myfifo (
	page,
	ad_busy,
	rd_addr,
	strb,
	rd_clk,
	mcu_rd,
	mcu_wr,
	mcu_a,
	dram_busy,
	rd_add,
	g_clk,
	ad_eoc,
	dog_en,
	ad_db,
	d,
	full_int,
	ad_cs,
	ad_wr,
	ad_rd,
	ad_sel,
	ad_conv,
	dsp_sram_ce,
	dsp_sram_oe,
	dsp_sram_we,
	dsp_flash_ce,
	dsp_flash_oe,
	dsp_flash_we,
	bus1_ce,
	bus1_dir,
	bus2_dir,
	can_cs,
	addr_cs,
	dsp_tck0,
	dsp_tck1,
	dsp_run,
	bus2_ce,
	dsp_rdy,
	dsp_rst,
	dsp_dram_ce,
	dsp_dram_oe,
	dsp_dram_rw,
	mcu_dram_ce,
	dir_4052,
	ad_sl);
input 	[3:0] page;
input 	ad_busy;
input 	[7:0] rd_addr;
input 	strb;
input 	rd_clk;
input 	mcu_rd;
input 	mcu_wr;
input 	[15:12] mcu_a;
input 	dram_busy;
input 	[15:12] rd_add;
input 	g_clk;
input 	ad_eoc;
input 	dog_en;
input 	[13:0] ad_db;
inout 	[15:0] d;
output 	full_int;
output 	ad_cs;
output 	ad_wr;
output 	ad_rd;
output 	ad_sel;
output 	ad_conv;
output 	dsp_sram_ce;
output 	dsp_sram_oe;
output 	dsp_sram_we;
output 	dsp_flash_ce;
output 	dsp_flash_oe;
output 	dsp_flash_we;
output 	bus1_ce;
output 	bus1_dir;
output 	bus2_dir;
output 	can_cs;
output 	addr_cs;
output 	dsp_tck0;
output 	dsp_tck1;
output 	dsp_run;
output 	bus2_ce;
output 	dsp_rdy;
output 	dsp_rst;
output 	dsp_dram_ce;
output 	dsp_dram_oe;
output 	dsp_dram_rw;
output 	mcu_dram_ce;
output 	dir_4052;
output 	[3:0] ad_sl;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("myfifo_v.sdo");
// synopsys translate_on

wire \inst1|int_reg_rtl_0|wysi_counter|q[6] ;
wire \inst2|reduce_nor~94 ;
wire \inst2|reduce_nor~96 ;
wire \inst1|int_reg_rtl_0|wysi_counter|q[0] ;
wire \inst1|delay[7] ;
wire \inst1|delay[11] ;
wire \inst1|delay[10] ;
wire \inst1|delay[9] ;
wire \inst1|delay[8] ;
wire \inst1|LessThan~373 ;
wire \inst1|delay[5] ;
wire \inst1|delay[6] ;
wire \inst1|delay[4] ;
wire \inst1|delay[3] ;
wire \inst1|delay[2] ;
wire \inst1|LessThan~374 ;
wire \inst1|LessThan~375 ;
wire \inst1|change_end~10 ;
wire \inst1|change_end ;
wire \inst1|change_end~11 ;
wire \inst|watch_reg~52 ;
wire \inst1|reduce_or~9 ;
wire \inst1|add_rtl_2|adder|result_node|cout[7] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[7] ;
wire \inst1|add_rtl_2|adder|result_node|cout[10] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[10] ;
wire \inst1|add_rtl_2|adder|result_node|cout[9] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[9] ;
wire \inst1|add_rtl_2|adder|result_node|cout[8] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[8] ;
wire \inst1|add_rtl_2|adder|result_node|cout[5] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[5] ;
wire \inst1|add_rtl_2|adder|result_node|cout[6] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[6] ;
wire \inst1|add_rtl_2|adder|result_node|cout[4] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[4] ;
wire \inst1|add_rtl_2|adder|result_node|cout[3] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[3] ;
wire \inst1|add_rtl_2|adder|result_node|cout[2] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[2] ;
wire \inst1|reduce_or~11 ;
wire \inst2|reduce_nor~99_cascout ;
wire \inst2|reduce_nor~99 ;
wire \inst2|reduce_nor~101 ;
wire \inst1|add_rtl_2|adder|unreg_res_node[11] ;
wire \inst1|Select~2343 ;
wire \inst1|add_rtl_2|adder|result_node|cout[1] ;
wire \inst1|add_rtl_2|adder|result_node|cs_buffer[1] ;
wire \inst2|coll_mem[4][13] ;
wire \inst2|coll_mem[7][13] ;
wire \inst2|coll_mem[0][13] ;
wire \inst2|coll_mem[3][13] ;
wire \inst2|coll_mem[4][12] ;
wire \inst2|coll_mem[7][12] ;
wire \inst2|coll_mem[0][12] ;
wire \inst2|coll_mem[3][12] ;
wire \inst2|coll_mem[4][11] ;
wire \inst2|coll_mem[7][11] ;
wire \inst2|coll_mem[0][11] ;
wire \inst2|coll_mem[3][11] ;
wire \inst2|coll_mem[4][10] ;
wire \inst2|coll_mem[7][10] ;
wire \inst2|coll_mem[0][10] ;
wire \inst2|coll_mem[3][10] ;
wire \inst2|coll_mem[4][9] ;
wire \inst2|coll_mem[7][9] ;
wire \inst2|coll_mem[0][9] ;
wire \inst2|coll_mem[3][9] ;
wire \inst2|coll_mem[4][8] ;
wire \inst2|coll_mem[7][8] ;
wire \inst2|coll_mem[0][8] ;
wire \inst2|coll_mem[3][8] ;
wire \inst2|coll_mem[4][7] ;
wire \inst2|coll_mem[7][7] ;
wire \inst2|coll_mem[0][7] ;
wire \inst2|coll_mem[3][7] ;
wire \inst2|coll_mem[4][6] ;
wire \inst2|coll_mem[7][6] ;
wire \inst2|coll_mem[0][6] ;
wire \inst2|coll_mem[3][6] ;
wire \inst2|coll_mem[4][5] ;
wire \inst2|coll_mem[7][5] ;
wire \inst2|coll_mem[0][5] ;
wire \inst2|coll_mem[3][5] ;
wire \inst2|coll_mem[4][4] ;
wire \inst2|coll_mem[7][4] ;
wire \inst2|coll_mem[0][4] ;
wire \inst2|coll_mem[3][4] ;
wire \inst2|coll_mem[4][3] ;
wire \inst2|coll_mem[7][3] ;
wire \inst2|coll_mem[0][3] ;
wire \inst2|coll_mem[3][3] ;
wire \inst2|coll_mem[4][2] ;
wire \inst2|coll_mem[7][2] ;
wire \inst2|coll_mem[0][2] ;
wire \inst2|coll_mem[3][2] ;
wire \inst2|coll_mem[4][1] ;
wire \inst2|coll_mem[7][1] ;
wire \inst2|coll_mem[0][1] ;
wire \inst2|coll_mem[3][1] ;
wire \inst2|coll_mem[4][0] ;
wire \inst2|coll_mem[7][0] ;
wire \inst2|coll_mem[0][0] ;
wire \inst2|coll_mem[3][0] ;
wire \inst1|wr_addr[2] ;
wire \inst1|wr_addr[0] ;
wire \inst1|wr_addr[1] ;
wire \inst2|coll_mem[5][13]~28 ;
wire \inst2|coll_mem[6][13]~14 ;
wire \inst2|coll_mem[4][13]~42 ;
wire \inst2|coll_mem[7][13]~0 ;
wire \inst2|coll_mem[2][13]~70 ;
wire \inst2|coll_mem[1][13]~84 ;
wire \inst2|coll_mem[0][13]~98 ;
wire \inst2|coll_mem[3][13]~56 ;
wire \inst1|delay[1] ;
wire \inst1|add_rtl_2|adder|result_node|cout[0] ;
wire \inst1|delay[0] ;
wire \inst2|d_out[13]~2394 ;
wire \inst2|d_out[13]~2436 ;
wire \inst1|Select~142 ;
wire \inst1|Select~138 ;
wire \inst2|d_out[12]~2396 ;
wire \inst2|d_out[12]~2437 ;
wire \inst2|d_out[11]~2398 ;
wire \inst2|d_out[11]~2438 ;
wire \inst2|d_out[10]~2400 ;
wire \inst2|d_out[10]~2439 ;
wire \inst2|d_out[9]~2402 ;
wire \inst2|d_out[9]~2440 ;
wire \inst2|d_out[8]~2404 ;
wire \inst2|d_out[8]~2441 ;
wire \inst2|d_out[7]~2406 ;
wire \inst2|d_out[7]~2442 ;
wire \inst2|d_out[6]~2408 ;
wire \inst2|d_out[6]~2443 ;
wire \inst2|d_out[5]~2410 ;
wire \inst2|d_out[5]~2444 ;
wire \inst2|d_out[4]~2412 ;
wire \inst2|d_out[4]~2445 ;
wire \inst2|d_out[3]~2414 ;
wire \inst2|d_out[3]~2446 ;
wire \inst2|d_out[2]~2416 ;
wire \inst2|d_out[2]~2447 ;
wire \inst2|d_out[1]~2418 ;
wire \inst2|d_out[1]~2448 ;
wire \inst2|d_out[0]~2420 ;
wire \inst2|d_out[0]~2449 ;
wire \inst1|delay~24 ;
wire \inst1|Select~91 ;
wire \inst|Select~155_cascout ;
wire \inst|Select~155 ;
wire \inst|step~4 ;
wire \inst|Select~2655 ;
wire \d~2 ;
wire \d~3 ;
wire \d~4 ;
wire \d~5 ;
wire \d~6 ;
wire \d~7 ;
wire \d~8 ;
wire \d~9 ;
wire \d~10 ;
wire \d~11 ;
wire \d~12 ;
wire \d~13 ;
wire \d~14 ;
wire \d~15 ;
wire \g_clk~dataout ;
wire \inst|step~18 ;
wire \inst|step~20 ;
wire \inst|Select~2626 ;
wire \inst|watch_reg[0] ;
wire \inst|add_rtl_1|adder|result_node|cout[0] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[1] ;
wire \inst|Select~2651 ;
wire \inst|watch_reg[1] ;
wire \inst|add_rtl_1|adder|result_node|cout[1] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[2] ;
wire \inst|Select~2650 ;
wire \inst|watch_reg[2] ;
wire \inst|add_rtl_1|adder|result_node|cout[2] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[3] ;
wire \inst|Select~2649 ;
wire \inst|watch_reg[3] ;
wire \inst|add_rtl_1|adder|result_node|cout[3] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[4] ;
wire \inst|Select~2648 ;
wire \inst|watch_reg[4] ;
wire \inst|add_rtl_1|adder|result_node|cout[4] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[5] ;
wire \inst|Select~2647 ;
wire \inst|watch_reg[5] ;
wire \inst|add_rtl_1|adder|result_node|cout[5] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[6] ;
wire \inst|Select~2635 ;
wire \inst|watch_reg[6] ;
wire \inst|add_rtl_1|adder|result_node|cout[6] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[7] ;
wire \inst|Select~2634 ;
wire \inst|watch_reg[7] ;
wire \inst|add_rtl_1|adder|result_node|cout[7] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[8] ;
wire \inst|Select~2633 ;
wire \inst|watch_reg[8] ;
wire \inst|add_rtl_1|adder|result_node|cout[8] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[9] ;
wire \inst|Select~2632 ;
wire \inst|watch_reg[9] ;
wire \inst|add_rtl_1|adder|result_node|cout[9] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[10] ;
wire \inst|Select~2631 ;
wire \inst|watch_reg[10] ;
wire \inst|add_rtl_1|adder|result_node|cout[10] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[11] ;
wire \inst|Select~2630 ;
wire \inst|watch_reg[11] ;
wire \inst|add_rtl_1|adder|result_node|cout[11] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[12] ;
wire \inst|Select~2629 ;
wire \inst|watch_reg[12] ;
wire \inst|add_rtl_1|adder|result_node|cout[12] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[13] ;
wire \inst|Select~2628 ;
wire \inst|watch_reg[13] ;
wire \inst|add_rtl_1|adder|result_node|cout[13] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[14] ;
wire \inst|Select~2627 ;
wire \inst|watch_reg[14] ;
wire \inst|add_rtl_1|adder|result_node|cout[14] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[15] ;
wire \inst|Select~2638 ;
wire \inst|watch_reg[15] ;
wire \inst|add_rtl_1|adder|result_node|cout[15] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[16] ;
wire \inst|Select~2639 ;
wire \inst|watch_reg[16] ;
wire \inst|add_rtl_1|adder|result_node|cout[16] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[17] ;
wire \inst|Select~2637 ;
wire \inst|watch_reg[17] ;
wire \inst|add_rtl_1|adder|result_node|cout[17] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[18] ;
wire \inst|Select~2644 ;
wire \inst|watch_reg[18] ;
wire \inst|add_rtl_1|adder|result_node|cout[18] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[19] ;
wire \inst|Select~2643 ;
wire \inst|watch_reg[19] ;
wire \inst|add_rtl_1|adder|result_node|cout[19] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[20] ;
wire \inst|Select~2642 ;
wire \inst|watch_reg[20] ;
wire \inst|add_rtl_1|adder|result_node|cout[20] ;
wire \inst|add_rtl_1|adder|result_node|cs_buffer[21] ;
wire \inst|Select~2641 ;