📄 myfifo_v.sdo

📁 VERILOG HDL 实际工控项目源码
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      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[6\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3700:3700:3700) (3700:3700:3700))
        (PORT datad (4600:4600:4600) (4600:4600:4600))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[6\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (4900:4900:4900) (4900:4900:4900))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[6\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3700:3700:3700) (3700:3700:3700))
        (PORT datad (4600:4600:4600) (4600:4600:4600))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[6\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (4900:4900:4900) (4900:4900:4900))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[6\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3900:3900:3900) (3900:3900:3900))
        (PORT datad (4400:4400:4400) (4400:4400:4400))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[6\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5100:5100:5100) (5100:5100:5100))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[6\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4200:4200:4200) (4200:4200:4200))
        (PORT datad (4400:4400:4400) (4400:4400:4400))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[6\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5400:5400:5400) (5400:5400:5400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3700:3700:3700) (3700:3700:3700))
        (PORT datad (4700:4700:4700) (4700:4700:4700))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (4900:4900:4900) (4900:4900:4900))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3800:3800:3800) (3800:3800:3800))
        (PORT datad (4700:4700:4700) (4700:4700:4700))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5000:5000:5000) (5000:5000:5000))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3800:3800:3800) (3800:3800:3800))
        (PORT datad (4700:4700:4700) (4700:4700:4700))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5000:5000:5000) (5000:5000:5000))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4200:4200:4200) (4200:4200:4200))
        (PORT datad (4600:4600:4600) (4600:4600:4600))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5400:5400:5400) (5400:5400:5400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4300:4300:4300) (4300:4300:4300))
        (PORT datad (3700:3700:3700) (3700:3700:3700))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5500:5500:5500) (5500:5500:5500))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4400:4400:4400) (4400:4400:4400))
        (PORT datad (3700:3700:3700) (3700:3700:3700))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5600:5600:5600) (5600:5600:5600))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3800:3800:3800) (3800:3800:3800))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5000:5000:5000) (5000:5000:5000))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4100:4100:4100) (4100:4100:4100))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5300:5300:5300) (5300:5300:5300))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4300:4300:4300) (4300:4300:4300))
        (PORT datad (4100:4100:4100) (4100:4100:4100))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5500:5500:5500) (5500:5500:5500))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4300:4300:4300) (4300:4300:4300))
        (PORT datad (4100:4100:4100) (4100:4100:4100))
上一页 1 2 3 45
💿 文件大小 1200 K
👤 上传用户 xfzzp_0321
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