📄 myfifo_v.sdo

📁 VERILOG HDL 实际工控项目源码
💻 SDO
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    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[10\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4900:4900:4900) (4900:4900:4900))
        (PORT datad (4300:4300:4300) (4300:4300:4300))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[10\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6100:6100:6100) (6100:6100:6100))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[10\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4600:4600:4600) (4600:4600:4600))
        (PORT datad (4300:4300:4300) (4300:4300:4300))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[10\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5800:5800:5800) (5800:5800:5800))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[9\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4500:4500:4500) (4500:4500:4500))
        (PORT datad (4200:4200:4200) (4200:4200:4200))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[9\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5700:5700:5700) (5700:5700:5700))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[9\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4500:4500:4500) (4500:4500:4500))
        (PORT datad (4200:4200:4200) (4200:4200:4200))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[9\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5700:5700:5700) (5700:5700:5700))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[9\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4700:4700:4700) (4700:4700:4700))
        (PORT datad (4200:4200:4200) (4200:4200:4200))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[9\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5900:5900:5900) (5900:5900:5900))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[9\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4600:4600:4600) (4600:4600:4600))
        (PORT datad (4100:4100:4100) (4100:4100:4100))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[9\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5800:5800:5800) (5800:5800:5800))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[8\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5200:5200:5200) (5200:5200:5200))
        (PORT datad (3700:3700:3700) (3700:3700:3700))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[8\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6400:6400:6400) (6400:6400:6400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[8\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5000:5000:5000) (5000:5000:5000))
        (PORT datad (3700:3700:3700) (3700:3700:3700))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[8\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6200:6200:6200) (6200:6200:6200))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[8\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4900:4900:4900) (4900:4900:4900))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[8\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6100:6100:6100) (6100:6100:6100))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[8\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4600:4600:4600) (4600:4600:4600))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[8\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5800:5800:5800) (5800:5800:5800))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[7\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5200:5200:5200) (5200:5200:5200))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[7\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6400:6400:6400) (6400:6400:6400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[7\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5200:5200:5200) (5200:5200:5200))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[7\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6400:6400:6400) (6400:6400:6400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[7\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5000:5000:5000) (5000:5000:5000))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[7\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6200:6200:6200) (6200:6200:6200))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[7\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5400:5400:5400) (5400:5400:5400))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[7\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6600:6600:6600) (6600:6600:6600))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
💿 文件大小 1200 K
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