📄 myfifo_v.sdo

📁 VERILOG HDL 实际工控项目源码
💻 SDO
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        (PORT dataa (5100:5100:5100) (5100:5100:5100))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[13\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6300:6300:6300) (6300:6300:6300))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[13\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5200:5200:5200) (5200:5200:5200))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[13\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6400:6400:6400) (6400:6400:6400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[13\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5100:5100:5100) (5100:5100:5100))
        (PORT datad (3600:3600:3600) (3600:3600:3600))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[13\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6300:6300:6300) (6300:6300:6300))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[13\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5200:5200:5200) (5200:5200:5200))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[13\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6400:6400:6400) (6400:6400:6400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[12\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5200:5200:5200) (5200:5200:5200))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[12\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6400:6400:6400) (6400:6400:6400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[12\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5300:5300:5300) (5300:5300:5300))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[12\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6500:6500:6500) (6500:6500:6500))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[12\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5100:5100:5100) (5100:5100:5100))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[12\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6300:6300:6300) (6300:6300:6300))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[12\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5400:5400:5400) (5400:5400:5400))
        (PORT datad (3800:3800:3800) (3800:3800:3800))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[12\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6600:6600:6600) (6600:6600:6600))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[11\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4200:4200:4200) (4200:4200:4200))
        (PORT datad (4300:4300:4300) (4300:4300:4300))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[11\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5400:5400:5400) (5400:5400:5400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[11\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4100:4100:4100) (4100:4100:4100))
        (PORT datad (4300:4300:4300) (4300:4300:4300))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[11\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5300:5300:5300) (5300:5300:5300))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[0\]\[11\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5200:5200:5200) (5200:5200:5200))
        (PORT datad (4000:4000:4000) (4000:4000:4000))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[0\]\[11\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6400:6400:6400) (6400:6400:6400))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[3\]\[11\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5500:5500:5500) (5500:5500:5500))
        (PORT datad (4000:4000:4000) (4000:4000:4000))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[3\]\[11\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (6700:6700:6700) (6700:6700:6700))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[4\]\[10\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4400:4400:4400) (4400:4400:4400))
        (PORT datad (4500:4500:4500) (4500:4500:4500))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[4\]\[10\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5600:5600:5600) (5600:5600:5600))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
    )
  )
  (CELL
    (CELLTYPE "flex10ke_asynch_lcell")
    (INSTANCE inst2\|coll_mem\[7\]\[10\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4500:4500:4500) (4500:4500:4500))
        (PORT datad (4500:4500:4500) (4500:4500:4500))
        (IOPATH datad regin (1200:1200:1200) (1200:1200:1200))
      )
    )
  )
  (CELL
    (CELLTYPE "flex10ke_lcell_register")
    (INSTANCE inst2\|coll_mem\[7\]\[10\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT clk (2500:2500:2500) (2500:2500:2500))
        (PORT dataa (5700:5700:5700) (5700:5700:5700))
        (IOPATH (posedge clk) regout (1100:1100:1100) (1100:1100:1100))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (2500:2500:2500))
      (SETUP dataa (posedge clk) (2500:2500:2500))
      (HOLD datain (posedge clk) (1600:1600:1600))
      (HOLD dataa (posedge clk) (1600:1600:1600))
💿 文件大小 1200 K
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