_primary.vhd

来自「VERILOG HDL 实际工控项目源码」· VHDL 代码 · 共 7 行

library verilog;
use verilog.vl_types.all;
entity prim_dffe is
    // This module cannot be connected to from
    // VHDL because it has unnamed ports.
end prim_dffe;