_primary.vhd

VERILOG HDL 实际工控项目源码

library verilog;
use verilog.vl_types.all;
entity myfifo is
    port(
        page            : in     vl_logic_vector(3 downto 0);
        we              : in     vl_logic;
        data            : in     vl_logic_vector(13 downto 0);
        rd_clk          : in     vl_logic;
        wr_clk          : in     vl_logic;
        wr_addr         : in     vl_logic_vector(6 downto 0);
        rd_addr         : in     vl_logic_vector(6 downto 0);
        d               : inout  vl_logic_vector(16 downto 0)
    );
end myfifo;