_primary.vhd

来自「VERILOG HDL 实际工控项目源码」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity and11 is
    port(
        y               : out    vl_logic_vector(10 downto 0);
        in1             : in     vl_logic_vector(10 downto 0)
    );
end and11;