myfifo.tan.rpt

VERILOG HDL 实际工控项目源码

; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                    ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------+-----------------------------+------------+------------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                        ; To                          ; From Clock ; To Clock   ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------+-----------------------------+------------+------------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 6.600 ns                                       ; ad_db[5]                    ; mydram:inst2|coll_mem[0][5] ;            ; g_clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 39.600 ns                                      ; mydram:inst2|coll_mem[4][0] ; d[0]                        ; g_clk      ;            ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 42.300 ns                                      ; rd_addr[1]                  ; d[0]                        ;            ;            ; 0            ;
; Worst-case th                ; N/A   ; None          ; 15.200 ns                                      ; d[13]                       ; mydram:inst2|rdy_reg[13]    ;            ; page[2]    ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 15.700 ns                                      ; ad_collect:inst1|full_int   ; full_int                    ; g_clk      ;            ; 0            ;
; Worst-case Minimum tpd       ; N/A   ; None          ; 18.000 ns                                      ; mcu_wr                      ; can_cs                      ;            ;            ; 0            ;
; Clock Setup: 'g_clk'         ; N/A   ; None          ; 33.90 MHz ( period = 29.500 ns )               ; watchdog:inst|watch_reg[7]  ; watchdog:inst|watch_reg[24] ; g_clk      ; g_clk      ; 0            ;
; Clock Setup: 'rd_add[14]'    ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; addr_code:inst5|dsp_run     ; addr_code:inst5|dsp_run     ; rd_add[14] ; rd_add[14] ; 0            ;
; Clock Setup: 'rd_add[13]'    ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; addr_code:inst5|dsp_run     ; addr_code:inst5|dsp_run     ; rd_add[13] ; rd_add[13] ; 0            ;
; Clock Setup: 'rd_add[15]'    ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; addr_code:inst5|dsp_run     ; addr_code:inst5|dsp_run     ; rd_add[15] ; rd_add[15] ; 0            ;
; Clock Setup: 'rd_add[12]'    ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; addr_code:inst5|dsp_run     ; addr_code:inst5|dsp_run     ; rd_add[12] ; rd_add[12] ; 0            ;
; Clock Setup: 'page[2]'       ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; addr_code:inst5|dsp_run     ; addr_code:inst5|dsp_run     ; page[2]    ; page[2]    ; 0            ;
; Clock Setup: 'strb'          ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; addr_code:inst5|dsp_run     ; addr_code:inst5|dsp_run     ; strb       ; strb       ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                             ;                             ;            ;            ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------+-----------------------------+------------+------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; g_clk           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; strb            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; rd_clk          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; page[2]         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; rd_add[12]      ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; rd_add[15]      ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; rd_add[13]      ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; rd_add[14]      ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'g_clk'                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------+-----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                        ; To                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------+-----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 33.90 MHz ( period = 29.500 ns )                    ; watchdog:inst|watch_reg[9]  ; watchdog:inst|watch_reg[24] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 33.90 MHz ( period = 29.500 ns )                    ; watchdog:inst|watch_reg[8]  ; watchdog:inst|watch_reg[24] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 33.90 MHz ( period = 29.500 ns )                    ; watchdog:inst|watch_reg[7]  ; watchdog:inst|watch_reg[24] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.25 MHz ( period = 29.200 ns )                    ; watchdog:inst|watch_reg[9]  ; watchdog:inst|watch_reg[12] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.25 MHz ( period = 29.200 ns )                    ; watchdog:inst|watch_reg[8]  ; watchdog:inst|watch_reg[12] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.25 MHz ( period = 29.200 ns )                    ; watchdog:inst|watch_reg[7]  ; watchdog:inst|watch_reg[12] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.36 MHz ( period = 29.100 ns )                    ; watchdog:inst|watch_reg[11] ; watchdog:inst|watch_reg[24] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.48 MHz ( period = 29.000 ns )                    ; watchdog:inst|watch_reg[10] ; watchdog:inst|watch_reg[24] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.72 MHz ( period = 28.800 ns )                    ; watchdog:inst|watch_reg[9]  ; watchdog:inst|watch_reg[22] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.72 MHz ( period = 28.800 ns )                    ; watchdog:inst|watch_reg[8]  ; watchdog:inst|watch_reg[22] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;
; N/A                                     ; 34.72 MHz ( period = 28.800 ns )                    ; watchdog:inst|watch_reg[7]  ; watchdog:inst|watch_reg[22] ; g_clk      ; g_clk    ; None                        ; None                      ; None                    ;