myfifo.tan.summary

VERILOG HDL 实际工控项目源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.600 ns
From           : ad_db[5]
To             : mydram:inst2|coll_mem[0][5]
From Clock     : 
To Clock       : g_clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 39.600 ns
From           : mydram:inst2|coll_mem[4][0]
To             : d[0]
From Clock     : g_clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 42.300 ns
From           : rd_addr[1]
To             : d[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 15.200 ns
From           : d[13]
To             : mydram:inst2|rdy_reg[13]
From Clock     : 
To Clock       : page[2]
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.700 ns
From           : ad_collect:inst1|full_int
To             : full_int
From Clock     : g_clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 18.000 ns
From           : mcu_wr
To             : can_cs
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'g_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 33.90 MHz ( period = 29.500 ns )
From           : watchdog:inst|watch_reg[7]
To             : watchdog:inst|watch_reg[24]
From Clock     : g_clk
To Clock       : g_clk
Failed Paths   : 0

Type           : Clock Setup: 'rd_add[14]'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : addr_code:inst5|dsp_run
To             : addr_code:inst5|dsp_run
From Clock     : rd_add[14]
To Clock       : rd_add[14]
Failed Paths   : 0

Type           : Clock Setup: 'rd_add[13]'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : addr_code:inst5|dsp_run
To             : addr_code:inst5|dsp_run
From Clock     : rd_add[13]
To Clock       : rd_add[13]
Failed Paths   : 0

Type           : Clock Setup: 'rd_add[15]'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : addr_code:inst5|dsp_run
To             : addr_code:inst5|dsp_run
From Clock     : rd_add[15]
To Clock       : rd_add[15]
Failed Paths   : 0

Type           : Clock Setup: 'rd_add[12]'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : addr_code:inst5|dsp_run
To             : addr_code:inst5|dsp_run
From Clock     : rd_add[12]
To Clock       : rd_add[12]
Failed Paths   : 0

Type           : Clock Setup: 'page[2]'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : addr_code:inst5|dsp_run
To             : addr_code:inst5|dsp_run
From Clock     : page[2]
To Clock       : page[2]
Failed Paths   : 0

Type           : Clock Setup: 'strb'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : addr_code:inst5|dsp_run
To             : addr_code:inst5|dsp_run
From Clock     : strb
To Clock       : strb
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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