myfifo.map.eqn

VERILOG HDL 实际工控项目源码

D1_rdy_reg[10] = DFFEA(D1_rdy_reg[10]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[12] is mydram:inst2|rdy_reg[12]
--operation mode is normal

D1_rdy_reg[12]_lut_out = A1L96;
D1_rdy_reg[12] = DFFEA(D1_rdy_reg[12]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[11] is mydram:inst2|rdy_reg[11]
--operation mode is normal

D1_rdy_reg[11]_lut_out = A1L07;
D1_rdy_reg[11] = DFFEA(D1_rdy_reg[11]_lut_out, D1_rdy_en, , , , , );


--D1L392 is mydram:inst2|reduce_nor~101
--operation mode is normal

D1L392 = (D1_rdy_reg[13] & D1_rdy_reg[10] & !D1_rdy_reg[12] & !D1_rdy_reg[11]) & CASCADE(D1L292);


--G1_unreg_res_node[25] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[25]
--operation mode is normal

G1_unreg_res_node[25] = J3_cout[24] $ B1_watch_reg[25];


--G2_unreg_res_node[11] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[11]
--operation mode is normal

G2_unreg_res_node[11] = J6_cout[10] $ C1_delay[11];


--C1L71 is ad_collect:inst1|Select~2343
--operation mode is normal

C1L71 = C1L85Q & (!C1_change_end # !C1L75Q) # !C1L85Q & !C1L51 & (!C1_change_end # !C1L75Q);


--C1L81 is ad_collect:inst1|Select~2345
--operation mode is normal

C1L81 = (C1_eoc_reg[1] & !C1_eoc_reg[0] # !C1L5 # !C1L36Q) & CASCADE(C1L71);


--J3_cs_buffer[5] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

J3_cs_buffer[5] = B1_watch_reg[5] $ J3_cout[4];

--J3_cout[5] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

J3_cout[5] = CARRY(B1_watch_reg[5] & J3_cout[4]);


--J6_cs_buffer[1] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

J6_cs_buffer[1] = C1_delay[1] $ J6_cout[0];

--J6_cout[1] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

J6_cout[1] = CARRY(C1_delay[1] & J6_cout[0]);


--D1_coll_mem[5][13] is mydram:inst2|coll_mem[5][13]
--operation mode is normal

D1_coll_mem[5][13]_lut_out = !ad_db[13];
D1_coll_mem[5][13] = DFFEA(D1_coll_mem[5][13]_lut_out, g_clk, , , D1L081, , );


--D1_coll_mem[6][13] is mydram:inst2|coll_mem[6][13]
--operation mode is normal

D1_coll_mem[6][13]_lut_out = !ad_db[13];
D1_coll_mem[6][13] = DFFEA(D1_coll_mem[6][13]_lut_out, g_clk, , , D1L691, , );


--D1_coll_mem[4][13] is mydram:inst2|coll_mem[4][13]
--operation mode is normal

D1_coll_mem[4][13]_lut_out = !ad_db[13];
D1_coll_mem[4][13] = DFFEA(D1_coll_mem[4][13]_lut_out, g_clk, , , D1L461, , );


--D1L3 is mydram:inst2|Mux~294
--operation mode is normal

D1L3 = rd_addr[1] & (rd_addr[0] # D1_coll_mem[6][13]) # !rd_addr[1] & !rd_addr[0] & D1_coll_mem[4][13];


--D1_coll_mem[7][13] is mydram:inst2|coll_mem[7][13]
--operation mode is normal

D1_coll_mem[7][13]_lut_out = !ad_db[13];
D1_coll_mem[7][13] = DFFEA(D1_coll_mem[7][13]_lut_out, g_clk, , , D1L212, , );


--D1L4 is mydram:inst2|Mux~295
--operation mode is normal

D1L4 = D1L3 & (D1_coll_mem[7][13] # !rd_addr[0]) # !D1L3 & D1_coll_mem[5][13] & rd_addr[0];


--D1_coll_mem[2][13] is mydram:inst2|coll_mem[2][13]
--operation mode is normal

D1_coll_mem[2][13]_lut_out = !ad_db[13];
D1_coll_mem[2][13] = DFFEA(D1_coll_mem[2][13]_lut_out, g_clk, , , D1L231, , );


--D1_coll_mem[1][13] is mydram:inst2|coll_mem[1][13]
--operation mode is normal

D1_coll_mem[1][13]_lut_out = !ad_db[13];
D1_coll_mem[1][13] = DFFEA(D1_coll_mem[1][13]_lut_out, g_clk, , , D1L611, , );


--D1_coll_mem[0][13] is mydram:inst2|coll_mem[0][13]
--operation mode is normal

D1_coll_mem[0][13]_lut_out = !ad_db[13];
D1_coll_mem[0][13] = DFFEA(D1_coll_mem[0][13]_lut_out, g_clk, , , D1L001, , );


--D1L1 is mydram:inst2|Mux~292
--operation mode is normal

D1L1 = rd_addr[0] & (rd_addr[1] # D1_coll_mem[1][13]) # !rd_addr[0] & !rd_addr[1] & D1_coll_mem[0][13];


--D1_coll_mem[3][13] is mydram:inst2|coll_mem[3][13]
--operation mode is normal

D1_coll_mem[3][13]_lut_out = !ad_db[13];
D1_coll_mem[3][13] = DFFEA(D1_coll_mem[3][13]_lut_out, g_clk, , , D1L841, , );


--D1L2 is mydram:inst2|Mux~293
--operation mode is normal

D1L2 = D1L1 & (D1_coll_mem[3][13] # !rd_addr[1]) # !D1L1 & D1_coll_mem[2][13] & rd_addr[1];


--D1L75 is mydram:inst2|Mux~616
--operation mode is normal

D1L75 = !rd_addr[3] & (rd_addr[2] & D1L4 # !rd_addr[2] & D1L2);


--D1_coll_mem[8][13] is mydram:inst2|coll_mem[8][13]
--operation mode is normal

D1_coll_mem[8][13]_lut_out = D1_rdy_reg[13];
D1_coll_mem[8][13] = DFFEA(D1_coll_mem[8][13]_lut_out, g_clk, , , , , );


--D1L85 is mydram:inst2|Mux~617
--operation mode is normal

D1L85 = D1L75 # rd_addr[3] & D1_coll_mem[8][13];


--D1L862 is mydram:inst2|d_out[13]~2422
--operation mode is normal

D1L862 = (E1_dsp_flash_oe # rd_add[14] # !D1L85 # !D1L372) & CASCADE(D1L962);


--D1_coll_mem[5][12] is mydram:inst2|coll_mem[5][12]
--operation mode is normal

D1_coll_mem[5][12]_lut_out = ad_db[12];
D1_coll_mem[5][12] = DFFEA(D1_coll_mem[5][12]_lut_out, g_clk, , , D1L081, , );


--D1_coll_mem[6][12] is mydram:inst2|coll_mem[6][12]
--operation mode is normal

D1_coll_mem[6][12]_lut_out = ad_db[12];
D1_coll_mem[6][12] = DFFEA(D1_coll_mem[6][12]_lut_out, g_clk, , , D1L691, , );


--D1_coll_mem[4][12] is mydram:inst2|coll_mem[4][12]
--operation mode is normal

D1_coll_mem[4][12]_lut_out = ad_db[12];
D1_coll_mem[4][12] = DFFEA(D1_coll_mem[4][12]_lut_out, g_clk, , , D1L461, , );


--D1L7 is mydram:inst2|Mux~298
--operation mode is normal

D1L7 = rd_addr[1] & (rd_addr[0] # D1_coll_mem[6][12]) # !rd_addr[1] & !rd_addr[0] & D1_coll_mem[4][12];


--D1_coll_mem[7][12] is mydram:inst2|coll_mem[7][12]
--operation mode is normal

D1_coll_mem[7][12]_lut_out = ad_db[12];
D1_coll_mem[7][12] = DFFEA(D1_coll_mem[7][12]_lut_out, g_clk, , , D1L212, , );


--D1L8 is mydram:inst2|Mux~299
--operation mode is normal

D1L8 = D1L7 & (D1_coll_mem[7][12] # !rd_addr[0]) # !D1L7 & D1_coll_mem[5][12] & rd_addr[0];


--D1_coll_mem[2][12] is mydram:inst2|coll_mem[2][12]
--operation mode is normal

D1_coll_mem[2][12]_lut_out = ad_db[12];
D1_coll_mem[2][12] = DFFEA(D1_coll_mem[2][12]_lut_out, g_clk, , , D1L231, , );


--D1_coll_mem[1][12] is mydram:inst2|coll_mem[1][12]
--operation mode is normal

D1_coll_mem[1][12]_lut_out = ad_db[12];
D1_coll_mem[1][12] = DFFEA(D1_coll_mem[1][12]_lut_out, g_clk, , , D1L611, , );


--D1_coll_mem[0][12] is mydram:inst2|coll_mem[0][12]
--operation mode is normal

D1_coll_mem[0][12]_lut_out = ad_db[12];
D1_coll_mem[0][12] = DFFEA(D1_coll_mem[0][12]_lut_out, g_clk, , , D1L001, , );


--D1L5 is mydram:inst2|Mux~296
--operation mode is normal

D1L5 = rd_addr[0] & (rd_addr[1] # D1_coll_mem[1][12]) # !rd_addr[0] & !rd_addr[1] & D1_coll_mem[0][12];


--D1_coll_mem[3][12] is mydram:inst2|coll_mem[3][12]
--operation mode is normal

D1_coll_mem[3][12]_lut_out = ad_db[12];
D1_coll_mem[3][12] = DFFEA(D1_coll_mem[3][12]_lut_out, g_clk, , , D1L841, , );


--D1L6 is mydram:inst2|Mux~297
--operation mode is normal

D1L6 = D1L5 & (D1_coll_mem[3][12] # !rd_addr[1]) # !D1L5 & D1_coll_mem[2][12] & rd_addr[1];


--D1L95 is mydram:inst2|Mux~618
--operation mode is normal

D1L95 = !rd_addr[3] & (rd_addr[2] & D1L8 # !rd_addr[2] & D1L6);


--D1_coll_mem[8][12] is mydram:inst2|coll_mem[8][12]
--operation mode is normal

D1_coll_mem[8][12]_lut_out = D1_rdy_reg[12];
D1_coll_mem[8][12] = DFFEA(D1_coll_mem[8][12]_lut_out, g_clk, , , , , );


--D1L06 is mydram:inst2|Mux~619
--operation mode is normal

D1L06 = D1L95 # rd_addr[3] & D1_coll_mem[8][12];


--D1L562 is mydram:inst2|d_out[12]~2423
--operation mode is normal

D1L562 = (E1_dsp_flash_oe # rd_add[14] # !D1L06 # !D1L372) & CASCADE(D1L662);


--D1_coll_mem[5][11] is mydram:inst2|coll_mem[5][11]
--operation mode is normal

D1_coll_mem[5][11]_lut_out = ad_db[11];
D1_coll_mem[5][11] = DFFEA(D1_coll_mem[5][11]_lut_out, g_clk, , , D1L081, , );


--D1_coll_mem[6][11] is mydram:inst2|coll_mem[6][11]
--operation mode is normal

D1_coll_mem[6][11]_lut_out = ad_db[11];
D1_coll_mem[6][11] = DFFEA(D1_coll_mem[6][11]_lut_out, g_clk, , , D1L691, , );


--D1_coll_mem[4][11] is mydram:inst2|coll_mem[4][11]
--operation mode is normal

D1_coll_mem[4][11]_lut_out = ad_db[11];
D1_coll_mem[4][11] = DFFEA(D1_coll_mem[4][11]_lut_out, g_clk, , , D1L461, , );


--D1L11 is mydram:inst2|Mux~302
--operation mode is normal

D1L11 = rd_addr[1] & (rd_addr[0] # D1_coll_mem[6][11]) # !rd_addr[1] & !rd_addr[0] & D1_coll_mem[4][11];


--D1_coll_mem[7][11] is mydram:inst2|coll_mem[7][11]
--operation mode is normal

D1_coll_mem[7][11]_lut_out = ad_db[11];
D1_coll_mem[7][11] = DFFEA(D1_coll_mem[7][11]_lut_out, g_clk, , , D1L212, , );


--D1L21 is mydram:inst2|Mux~303
--operation mode is normal

D1L21 = D1L11 & (D1_coll_mem[7][11] # !rd_addr[0]) # !D1L11 & D1_coll_mem[5][11] & rd_addr[0];


--D1_coll_mem[2][11] is mydram:inst2|coll_mem[2][11]
--operation mode is normal

D1_coll_mem[2][11]_lut_out = ad_db[11];
D1_coll_mem[2][11] = DFFEA(D1_coll_mem[2][11]_lut_out, g_clk, , , D1L231, , );


--D1_coll_mem[1][11] is mydram:inst2|coll_mem[1][11]
--operation mode is normal

D1_coll_mem[1][11]_lut_out = ad_db[11];
D1_coll_mem[1][11] = DFFEA(D1_coll_mem[1][11]_lut_out, g_clk, , , D1L611, , );


--D1_coll_mem[0][11] is mydram:inst2|coll_mem[0][11]
--operation mode is normal

D1_coll_mem[0][11]_lut_out = ad_db[11];
D1_coll_mem[0][11] = DFFEA(D1_coll_mem[0][11]_lut_out, g_clk, , , D1L001, , );


--D1L9 is mydram:inst2|Mux~300
--operation mode is normal

D1L9 = rd_addr[0] & (rd_addr[1] # D1_coll_mem[1][11]) # !rd_addr[0] & !rd_addr[1] & D1_coll_mem[0][11];


--D1_coll_mem[3][11] is mydram:inst2|coll_mem[3][11]
--operation mode is normal

D1_coll_mem[3][11]_lut_out = ad_db[11];
D1_coll_mem[3][11] = DFFEA(D1_coll_mem[3][11]_lut_out, g_clk, , , D1L841, , );


--D1L01 is mydram:inst2|Mux~301
--operation mode is normal

D1L01 = D1L9 & (D1_coll_mem[3][11] # !rd_addr[1]) # !D1L9 & D1_coll_mem[2][11] & rd_addr[1];


--D1L16 is mydram:inst2|Mux~620
--operation mode is normal

D1L16 = !rd_addr[3] & (rd_addr[2] & D1L21 # !rd_addr[2] & D1L01);


--D1_coll_mem[8][11] is mydram:inst2|coll_mem[8][11]
--operation mode is normal

D1_coll_mem[8][11]_lut_out = D1_rdy_reg[11];
D1_coll_mem[8][11] = DFFEA(D1_coll_mem[8][11]_lut_out, g_clk, , , , , );


--D1L26 is mydram:inst2|Mux~621
--operation mode is normal

D1L26 = D1L16 # rd_addr[3] & D1_coll_mem[8][11];


--D1L262 is mydram:inst2|d_out[11]~2424
--operation mode is normal

D1L262 = (E1_dsp_flash_oe # rd_add[14] # !D1L26 # !D1L372) & CASCADE(D1L362);


--D1_coll_mem[5][10] is mydram:inst2|coll_mem[5][10]
--operation mode is normal

D1_coll_mem[5][10]_lut_out = ad_db[10];
D1_coll_mem[5][10] = DFFEA(D1_coll_mem[5][10]_lut_out, g_clk, , , D1L081, , );


--D1_coll_mem[6][10] is mydram:inst2|coll_mem[6][10]
--operation mode is normal

D1_coll_mem[6][10]_lut_out = ad_db[10];
D1_coll_mem[6][10] = DFFEA(D1_coll_mem[6][10]_lut_out, g_clk, , , D1L691, , );


--D1_coll_mem[4][10] is mydram:inst2|coll_mem[4][10]
--operation mode is normal

D1_coll_mem[4][10]_lut_out = ad_db[10];
D1_coll_mem[4][10] = DFFEA(D1_coll_mem[4][10]_lut_out, g_clk, , , D1L461, , );


--D1L51 is mydram:inst2|Mux~306
--operation mode is normal

D1L51 = rd_addr[1] & (rd_addr[0] # D1_coll_mem[6][10]) # !rd_addr[1] & !rd_addr[0] & D1_coll_mem[4][10];


--D1_coll_mem[7][10] is mydram:inst2|coll_mem[7][10]
--operation mode is normal

D1_coll_mem[7][10]_lut_out = ad_db[10];
D1_coll_mem[7][10] = DFFEA(D1_coll_mem[7][10]_lut_out, g_clk, , , D1L212, , );


--D1L61 is mydram:inst2|Mux~307
--operation mode is normal

D1L61 = D1L51 & (D1_coll_mem[7][10] # !rd_addr[0]) # !D1L51 & D1_coll_mem[5][10] & rd_addr[0];


--D1_coll_mem[2][10] is mydram:inst2|coll_mem[2][10]
--operation mode is normal

D1_coll_mem[2][10]_lut_out = ad_db[10];
D1_coll_mem[2][10] = DFFEA(D1_coll_mem[2][10]_lut_out, g_clk, , , D1L231, , );


--D1_coll_mem[1][10] is mydram:inst2|coll_mem[1][10]
--operation mode is normal

D1_coll_mem[1][10]_lut_out = ad_db[10];
D1_coll_mem[1][10] = DFFEA(D1_coll_mem[1][10]_lut_out, g_clk, , , D1L611, , );


--D1_coll_mem[0][10] is mydram:inst2|coll_mem[0][10]
--operation mode is normal

D1_coll_mem[0][10]_lut_out = ad_db[10];
D1_coll_mem[0][10] = DFFEA(D1_coll_mem[0][10]_lut_out, g_clk, , , D1L001, , );


--D1L31 is mydram:inst2|Mux~304
--operation mode is normal

D1L31 = rd_addr[0] & (rd_addr[1] # D1_coll_mem[1][10]) # !rd_addr[0] & !rd_addr[1] & D1_coll_mem[0][10];


--D1_coll_mem[3][10] is mydram:inst2|coll_mem[3][10]
--operation mode is normal

D1_coll_mem[3][10]_lut_out = ad_db[10];
D1_coll_mem[3][10] = DFFEA(D1_coll_mem[3][10]_lut_out, g_clk, , , D1L841, , );


--D1L41 is mydram:inst2|Mux~305
--operation mode is normal

D1L41 = D1L31 & (D1_coll_mem[3][10] # !rd_addr[1]) # !D1L31 & D1_coll_mem[2][10] & rd_addr[1];