myfifo.map.eqn

VERILOG HDL 实际工控项目源码

--B1L84Q is watchdog:inst|step~21
--operation mode is normal

B1L84Q_lut_out = B1L84Q # B1L64Q & (B1_watch_reg[25] # !B1L7);
B1L84Q = DFFEA(B1L84Q_lut_out, g_clk, , , , , );


--B1_dog_reg[1] is watchdog:inst|dog_reg[1]
--operation mode is normal

B1_dog_reg[1]_lut_out = B1_dog_reg[0] # !dog_en;
B1_dog_reg[1] = DFFEA(B1_dog_reg[1]_lut_out, g_clk, !B1_rst, , , , );


--B1_dog_reg[0] is watchdog:inst|dog_reg[0]
--operation mode is normal

B1_dog_reg[0]_lut_out = B1_dog_clk & dog_en;
B1_dog_reg[0] = DFFEA(B1_dog_reg[0]_lut_out, g_clk, !B1_rst, , , , );


--B1L01 is watchdog:inst|Select~2625
--operation mode is normal

B1L01 = B1L84Q & (B1_dog_reg[1] $ !B1_dog_reg[0]);


--B1_watch_reg[14] is watchdog:inst|watch_reg[14]
--operation mode is normal

B1_watch_reg[14]_lut_out = B1L21 # B1_watch_reg[14] & (B1L74Q # !B1L54Q);
B1_watch_reg[14] = DFFEA(B1_watch_reg[14]_lut_out, g_clk, , , , , );


--B1_watch_reg[13] is watchdog:inst|watch_reg[13]
--operation mode is normal

B1_watch_reg[13]_lut_out = B1L31 # B1_watch_reg[13] & (B1L74Q # !B1L54Q);
B1_watch_reg[13] = DFFEA(B1_watch_reg[13]_lut_out, g_clk, , , , , );


--B1_watch_reg[12] is watchdog:inst|watch_reg[12]
--operation mode is normal

B1_watch_reg[12]_lut_out = B1L41 # B1_watch_reg[12] & (B1L74Q # !B1L54Q);
B1_watch_reg[12] = DFFEA(B1_watch_reg[12]_lut_out, g_clk, , , , , );


--B1_watch_reg[11] is watchdog:inst|watch_reg[11]
--operation mode is normal

B1_watch_reg[11]_lut_out = B1L51 # B1_watch_reg[11] & (B1L74Q # !B1L54Q);
B1_watch_reg[11] = DFFEA(B1_watch_reg[11]_lut_out, g_clk, , , , , );


--B1L1 is watchdog:inst|LessThan~397
--operation mode is normal

B1L1 = !B1_watch_reg[11] # !B1_watch_reg[12] # !B1_watch_reg[13] # !B1_watch_reg[14];


--B1_watch_reg[10] is watchdog:inst|watch_reg[10]
--operation mode is normal

B1_watch_reg[10]_lut_out = B1L61 # B1_watch_reg[10] & (B1L74Q # !B1L54Q);
B1_watch_reg[10] = DFFEA(B1_watch_reg[10]_lut_out, g_clk, , , , , );


--B1_watch_reg[9] is watchdog:inst|watch_reg[9]
--operation mode is normal

B1_watch_reg[9]_lut_out = B1L71 # B1_watch_reg[9] & (B1L74Q # !B1L54Q);
B1_watch_reg[9] = DFFEA(B1_watch_reg[9]_lut_out, g_clk, , , , , );


--B1_watch_reg[8] is watchdog:inst|watch_reg[8]
--operation mode is normal

B1_watch_reg[8]_lut_out = B1L81 # B1_watch_reg[8] & (B1L74Q # !B1L54Q);
B1_watch_reg[8] = DFFEA(B1_watch_reg[8]_lut_out, g_clk, , , , , );


--B1_watch_reg[7] is watchdog:inst|watch_reg[7]
--operation mode is normal

B1_watch_reg[7]_lut_out = B1L91 # B1_watch_reg[7] & (B1L74Q # !B1L54Q);
B1_watch_reg[7] = DFFEA(B1_watch_reg[7]_lut_out, g_clk, , , , , );


--B1L2 is watchdog:inst|LessThan~398
--operation mode is normal

B1L2 = !B1_watch_reg[10] & !B1_watch_reg[9] & !B1_watch_reg[8] & !B1_watch_reg[7];


--B1_watch_reg[6] is watchdog:inst|watch_reg[6]
--operation mode is normal

B1_watch_reg[6]_lut_out = B1L02 # B1_watch_reg[6] & (B1L74Q # !B1L54Q);
B1_watch_reg[6] = DFFEA(B1_watch_reg[6]_lut_out, g_clk, , , , , );


--B1L3 is watchdog:inst|LessThan~399
--operation mode is normal

B1L3 = B1L1 # B1L2 & !B1_watch_reg[6];


--B1_watch_reg[23] is watchdog:inst|watch_reg[23]
--operation mode is normal

B1_watch_reg[23]_lut_out = B1L12 # B1_watch_reg[23] & (B1L74Q # !B1L54Q);
B1_watch_reg[23] = DFFEA(B1_watch_reg[23]_lut_out, g_clk, , , , , );


--B1_watch_reg[17] is watchdog:inst|watch_reg[17]
--operation mode is normal

B1_watch_reg[17]_lut_out = B1L22 # B1_watch_reg[17] & (B1L74Q # !B1L54Q);
B1_watch_reg[17] = DFFEA(B1_watch_reg[17]_lut_out, g_clk, , , , , );


--B1_watch_reg[15] is watchdog:inst|watch_reg[15]
--operation mode is normal

B1_watch_reg[15]_lut_out = B1L32 # B1_watch_reg[15] & (B1L74Q # !B1L54Q);
B1_watch_reg[15] = DFFEA(B1_watch_reg[15]_lut_out, g_clk, , , , , );


--B1L4 is watchdog:inst|LessThan~400
--operation mode is normal

B1L4 = B1L3 & !B1_watch_reg[23] & !B1_watch_reg[17] & !B1_watch_reg[15];


--B1_watch_reg[16] is watchdog:inst|watch_reg[16]
--operation mode is normal

B1_watch_reg[16]_lut_out = B1L42 # B1_watch_reg[16] & (B1L74Q # !B1L54Q);
B1_watch_reg[16] = DFFEA(B1_watch_reg[16]_lut_out, g_clk, , , , , );


--B1_watch_reg[22] is watchdog:inst|watch_reg[22]
--operation mode is normal

B1_watch_reg[22]_lut_out = B1L52 # B1_watch_reg[22] & (B1L74Q # !B1L54Q);
B1_watch_reg[22] = DFFEA(B1_watch_reg[22]_lut_out, g_clk, , , , , );


--B1_watch_reg[21] is watchdog:inst|watch_reg[21]
--operation mode is normal

B1_watch_reg[21]_lut_out = B1L62 # B1_watch_reg[21] & (B1L74Q # !B1L54Q);
B1_watch_reg[21] = DFFEA(B1_watch_reg[21]_lut_out, g_clk, , , , , );


--B1L5 is watchdog:inst|LessThan~401
--operation mode is normal

B1L5 = !B1_watch_reg[17] & !B1_watch_reg[16] # !B1_watch_reg[21] # !B1_watch_reg[22];


--B1_watch_reg[20] is watchdog:inst|watch_reg[20]
--operation mode is normal

B1_watch_reg[20]_lut_out = B1L72 # B1_watch_reg[20] & (B1L74Q # !B1L54Q);
B1_watch_reg[20] = DFFEA(B1_watch_reg[20]_lut_out, g_clk, , , , , );


--B1_watch_reg[19] is watchdog:inst|watch_reg[19]
--operation mode is normal

B1_watch_reg[19]_lut_out = B1L82 # B1_watch_reg[19] & (B1L74Q # !B1L54Q);
B1_watch_reg[19] = DFFEA(B1_watch_reg[19]_lut_out, g_clk, , , , , );


--B1_watch_reg[18] is watchdog:inst|watch_reg[18]
--operation mode is normal

B1_watch_reg[18]_lut_out = B1L92 # B1_watch_reg[18] & (B1L74Q # !B1L54Q);
B1_watch_reg[18] = DFFEA(B1_watch_reg[18]_lut_out, g_clk, , , , , );


--B1L6 is watchdog:inst|LessThan~402
--operation mode is normal

B1L6 = B1L5 # !B1_watch_reg[18] # !B1_watch_reg[19] # !B1_watch_reg[20];


--B1_watch_reg[24] is watchdog:inst|watch_reg[24]
--operation mode is normal

B1_watch_reg[24]_lut_out = B1L03 # B1_watch_reg[24] & (B1L74Q # !B1L54Q);
B1_watch_reg[24] = DFFEA(B1_watch_reg[24]_lut_out, g_clk, , , , , );


--B1L7 is watchdog:inst|LessThan~403
--operation mode is normal

B1L7 = B1L4 # B1L6 & !B1_watch_reg[23] # !B1_watch_reg[24];


--B1_watch_reg[25] is watchdog:inst|watch_reg[25]
--operation mode is normal

B1_watch_reg[25]_lut_out = B1L13 # B1_watch_reg[25] & (B1L74Q # !B1L54Q);
B1_watch_reg[25] = DFFEA(B1_watch_reg[25]_lut_out, g_clk, , , , , );


--B1L8 is watchdog:inst|Select~50
--operation mode is normal

B1L8 = B1L01 & (B1_rst $ (B1_watch_reg[25] # !B1L7));


--B1L64Q is watchdog:inst|step~19
--operation mode is normal

B1L64Q_lut_out = B1L74Q # B1L64Q & B1L7 & !B1_watch_reg[25];
B1L64Q = DFFEA(B1L64Q_lut_out, g_clk, , , , , );


--B1L11 is watchdog:inst|Select~2626
--operation mode is normal

B1L11 = B1L64Q & B1L7 & !B1_watch_reg[25];


--B1_feed_dog is watchdog:inst|feed_dog
--operation mode is normal

B1_feed_dog = rd_add[14] & rd_add[13] & E1L5;


--C1L15 is ad_collect:inst1|int_reg~34
--operation mode is normal

C1L15 = C1L2 # !L1_q[7] & L1L82 # !C1L25;


--L1_q[0] is ad_collect:inst1|lpm_counter:int_reg_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

L1_q[0]_lut_out = (!L1_q[0]) & C1L15;
L1_q[0] = DFFEA(L1_q[0]_lut_out, g_clk, !B1_rst, , , , );

--L1L3 is ad_collect:inst1|lpm_counter:int_reg_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

L1L3 = CARRY(L1_q[0]);


--C1_delay[7] is ad_collect:inst1|delay[7]
--operation mode is normal

C1_delay[7]_lut_out = C1L41 & (J6_cs_buffer[7] # C1_delay[7] & C1L35) # !C1L41 & C1_delay[7] & C1L35;
C1_delay[7] = DFFEA(C1_delay[7]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[11] is ad_collect:inst1|delay[11]
--operation mode is normal

C1_delay[11]_lut_out = C1L41 & (G2_unreg_res_node[11] # C1_delay[11] & C1L35) # !C1L41 & C1_delay[11] & C1L35;
C1_delay[11] = DFFEA(C1_delay[11]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[10] is ad_collect:inst1|delay[10]
--operation mode is normal

C1_delay[10]_lut_out = C1L41 & (J6_cs_buffer[10] # C1_delay[10] & C1L35) # !C1L41 & C1_delay[10] & C1L35;
C1_delay[10] = DFFEA(C1_delay[10]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[9] is ad_collect:inst1|delay[9]
--operation mode is normal

C1_delay[9]_lut_out = C1L41 & (J6_cs_buffer[9] # C1_delay[9] & C1L35) # !C1L41 & C1_delay[9] & C1L35;
C1_delay[9] = DFFEA(C1_delay[9]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[8] is ad_collect:inst1|delay[8]
--operation mode is normal

C1_delay[8]_lut_out = C1L41 & (J6_cs_buffer[8] # C1_delay[8] & C1L35) # !C1L41 & C1_delay[8] & C1L35;
C1_delay[8] = DFFEA(C1_delay[8]_lut_out, g_clk, !B1_rst, , , , );


--C1L3 is ad_collect:inst1|LessThan~373
--operation mode is normal

C1L3 = C1_delay[11] # C1_delay[10] # C1_delay[9] # C1_delay[8];


--C1_delay[5] is ad_collect:inst1|delay[5]
--operation mode is normal

C1_delay[5]_lut_out = C1L41 & (J6_cs_buffer[5] # C1_delay[5] & C1L35) # !C1L41 & C1_delay[5] & C1L35;
C1_delay[5] = DFFEA(C1_delay[5]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[6] is ad_collect:inst1|delay[6]
--operation mode is normal

C1_delay[6]_lut_out = C1L41 & (J6_cs_buffer[6] # C1_delay[6] & C1L35) # !C1L41 & C1_delay[6] & C1L35;
C1_delay[6] = DFFEA(C1_delay[6]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[4] is ad_collect:inst1|delay[4]
--operation mode is normal

C1_delay[4]_lut_out = C1L41 & (J6_cs_buffer[4] # C1_delay[4] & C1L35) # !C1L41 & C1_delay[4] & C1L35;
C1_delay[4] = DFFEA(C1_delay[4]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[3] is ad_collect:inst1|delay[3]
--operation mode is normal

C1_delay[3]_lut_out = C1L41 & (J6_cs_buffer[3] # C1_delay[3] & C1L35) # !C1L41 & C1_delay[3] & C1L35;
C1_delay[3] = DFFEA(C1_delay[3]_lut_out, g_clk, !B1_rst, , , , );


--C1_delay[2] is ad_collect:inst1|delay[2]
--operation mode is normal

C1_delay[2]_lut_out = C1L41 & (J6_cs_buffer[2] # C1_delay[2] & C1L35) # !C1L41 & C1_delay[2] & C1L35;
C1_delay[2] = DFFEA(C1_delay[2]_lut_out, g_clk, !B1_rst, , , , );


--C1L4 is ad_collect:inst1|LessThan~374
--operation mode is normal

C1L4 = C1_delay[6] & (C1_delay[4] # C1_delay[3] # C1_delay[2]);


--C1L5 is ad_collect:inst1|LessThan~375
--operation mode is normal

C1L5 = C1_delay[7] # C1L3 # C1_delay[5] & C1L4;


--C1L41 is ad_collect:inst1|Select~2336
--operation mode is normal

C1L41 = C1L36Q & !C1L5 & (C1_eoc_reg[0] # !C1_eoc_reg[1]);


--C1_counter[1] is ad_collect:inst1|counter[1]
--operation mode is normal

C1_counter[1]_lut_out = C1L7 # C1_counter[1] & (C1L61 # C1L45);
C1_counter[1] = DFFEA(C1_counter[1]_lut_out, g_clk, !B1_rst, , , , );


--C1_counter[0] is ad_collect:inst1|counter[0]
--operation mode is normal

C1_counter[0]_lut_out = C1_counter[0] & (C1L61 # C1L45) # !C1_counter[0] & C1L95Q;
C1_counter[0] = DFFEA(C1_counter[0]_lut_out, g_clk, !B1_rst, , , , );


--C1L32 is ad_collect:inst1|change_end~10
--operation mode is normal

C1L32 = C1_counter[1] & C1_counter[0];


--C1_collect_reg[0] is ad_collect:inst1|collect_reg[0]
--operation mode is normal

C1_collect_reg[0]_lut_out = !C1_full_int;
C1_collect_reg[0] = DFFEA(C1_collect_reg[0]_lut_out, g_clk, !B1_rst, , , , );


--C1_collect_reg[1] is ad_collect:inst1|collect_reg[1]
--operation mode is normal

C1_collect_reg[1]_lut_out = C1_collect_reg[0];
C1_collect_reg[1] = DFFEA(C1_collect_reg[1]_lut_out, g_clk, !B1_rst, , , , );


--C1L51 is ad_collect:inst1|Select~2338
--operation mode is normal

C1L51 = C1_collect_reg[0] & !C1_collect_reg[1];


--C1_change_end is ad_collect:inst1|change_end
--operation mode is normal

C1_change_end_lut_out = !C1_change_end;
C1_change_end = DFFEA(C1_change_end_lut_out, g_clk, !B1_rst, , C1L42, , );


--C1L42 is ad_collect:inst1|change_end~11
--operation mode is normal

C1L42 = C1L95Q & C1_counter[1] & C1_counter[0];


--D1L372 is mydram:inst2|rd_en~42
--operation mode is normal

D1L372 = rd_add[13] & rd_add[15] & rd_add[12] & !page[2];


--D1_rdy_en is mydram:inst2|rdy_en
--operation mode is normal

D1_rdy_en = strb # rd_clk # !rd_add[14] # !D1L372;


--B1L54Q is watchdog:inst|step~18
--operation mode is normal

B1L54Q_lut_out = VCC;
B1L54Q = DFFEA(B1L54Q_lut_out, g_clk, , , , , );


--J3_cs_buffer[14] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

J3_cs_buffer[14] = B1_watch_reg[14] $ J3_cout[13];

--J3_cout[14] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

J3_cout[14] = CARRY(B1_watch_reg[14] & J3_cout[13]);


--B1L67 is watchdog:inst|watch_reg~52
--operation mode is normal

B1L67 = B1L7 & !B1_watch_reg[25] & (B1_dog_reg[1] $ !B1_dog_reg[0]);


--B1L21 is watchdog:inst|Select~2627
--operation mode is normal

B1L21 = J3_cs_buffer[14] & (B1L11 # B1L84Q & B1L67);


--J3_cs_buffer[13] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

J3_cs_buffer[13] = B1_watch_reg[13] $ J3_cout[12];

--J3_cout[13] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

J3_cout[13] = CARRY(B1_watch_reg[13] & J3_cout[12]);


--B1L31 is watchdog:inst|Select~2628
--operation mode is normal

B1L31 = J3_cs_buffer[13] & (B1L11 # B1L84Q & B1L67);


--J3_cs_buffer[12] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

J3_cs_buffer[12] = B1_watch_reg[12] $ J3_cout[11];