songer.hier_info

基于FPGA的乐曲硬件演奏电路设计的实现

|Songer
CLK12MHZ => speakera:u3.clk
CLK8HZ => notetabs:u1.clk
CODE1[0] <= tonetaba:u2.CODE[0]
CODE1[1] <= tonetaba:u2.CODE[1]
CODE1[2] <= tonetaba:u2.CODE[2]
CODE1[3] <= tonetaba:u2.CODE[3]
HIGH1 <= tonetaba:u2.HIGH
SPKOUT <= speakera:u3.SpkS


|Songer|NoteTabs:u1
clk => Counter[6].CLK
clk => Counter[5].CLK
clk => Counter[4].CLK
clk => Counter[3].CLK
clk => Counter[2].CLK
clk => Counter[1].CLK
clk => Counter[0].CLK
clk => music:u1.inclock
clk => Counter[7].CLK
ToneIndex[0] <= music:u1.q[0]
ToneIndex[1] <= music:u1.q[1]
ToneIndex[2] <= music:u1.q[2]
ToneIndex[3] <= music:u1.q[3]


|Songer|NoteTabs:u1|music:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]


|Songer|NoteTabs:u1|music:u1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_des:auto_generated.address_a[0]
address_a[1] => altsyncram_des:auto_generated.address_a[1]
address_a[2] => altsyncram_des:auto_generated.address_a[2]
address_a[3] => altsyncram_des:auto_generated.address_a[3]
address_a[4] => altsyncram_des:auto_generated.address_a[4]
address_a[5] => altsyncram_des:auto_generated.address_a[5]
address_a[6] => altsyncram_des:auto_generated.address_a[6]
address_a[7] => altsyncram_des:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_des:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_des:auto_generated.q_a[0]
q_a[1] <= altsyncram_des:auto_generated.q_a[1]
q_a[2] <= altsyncram_des:auto_generated.q_a[2]
q_a[3] <= altsyncram_des:auto_generated.q_a[3]
q_b[0] <= <UNC>


|Songer|NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated
address_a[0] => altsyncram_j6a2:altsyncram1.address_a[0]
address_a[1] => altsyncram_j6a2:altsyncram1.address_a[1]
address_a[2] => altsyncram_j6a2:altsyncram1.address_a[2]
address_a[3] => altsyncram_j6a2:altsyncram1.address_a[3]
address_a[4] => altsyncram_j6a2:altsyncram1.address_a[4]
address_a[5] => altsyncram_j6a2:altsyncram1.address_a[5]
address_a[6] => altsyncram_j6a2:altsyncram1.address_a[6]
address_a[7] => altsyncram_j6a2:altsyncram1.address_a[7]
clock0 => altsyncram_j6a2:altsyncram1.clock0
q_a[0] <= altsyncram_j6a2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_j6a2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_j6a2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_j6a2:altsyncram1.q_a[3]


|Songer|NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE


|Songer|NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= ram_rom_incr_addr~1.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~7.DATAB
data_read[1] => ram_rom_data_reg~6.DATAB
data_read[2] => ram_rom_data_reg~5.DATAB
data_read[3] => ram_rom_data_reg~4.DATAB
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ram_rom_incr_write_addr_reg.CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => bypass_reg_out.CLK
raw_tck => is_in_use_reg.CLK
raw_tck => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TCK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => tck_usr.DATAIN
tdi => ram_rom_addr_reg~0.DATAB
tdi => ram_rom_data_reg~0.DATAB
tdi => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TDI
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.USR1
usr1 => dr_scan.IN0
usr1 => name_gen~0.IN0
jtag_state_cdr => name_gen~1.IN1
jtag_state_sdr => sdr.IN0
jtag_state_sdr => name_gen~1.IN0
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.SHIFT
jtag_state_e1dr => e1dr.IN1
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.UPDATE
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => dr_scan.IN1
ena => name_gen~0.IN1
ena => bypass_reg_out.ENA
ir_in[0] => ram_rom_addr_reg[6].ACLR
ir_in[0] => ram_rom_addr_reg[5].ACLR
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => ir_loaded_address_reg[3].ACLR
ir_in[0] => ir_loaded_address_reg[2].ACLR
ir_in[0] => ir_loaded_address_reg[1].ACLR
ir_in[0] => ir_loaded_address_reg[0].ACLR
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => ram_rom_addr_reg[7].ACLR
ir_in[1] => process1~0.IN1
ir_in[1] => process1~2.IN0
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[2] => process1~0.IN0
ir_in[2] => ram_rom_incr_addr~1.IN1
ir_in[3] => process0~0.IN1
ir_in[3] => process1~3.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => process5~0.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
irq <= <GND>
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|Songer|NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
ROM_DATA[0] => Mux~0.IN134
ROM_DATA[0] => Mux~1.IN134
ROM_DATA[0] => Mux~2.IN134
ROM_DATA[0] => Mux~3.IN134
ROM_DATA[1] => Mux~0.IN133
ROM_DATA[1] => Mux~1.IN133
ROM_DATA[1] => Mux~2.IN133
ROM_DATA[1] => Mux~3.IN133
ROM_DATA[2] => Mux~0.IN132
ROM_DATA[2] => Mux~1.IN132
ROM_DATA[2] => Mux~2.IN132
ROM_DATA[2] => Mux~3.IN132
ROM_DATA[3] => Mux~0.IN131
ROM_DATA[3] => Mux~1.IN131
ROM_DATA[3] => Mux~2.IN131
ROM_DATA[3] => Mux~3.IN131
ROM_DATA[4] => Mux~0.IN130
ROM_DATA[4] => Mux~1.IN130
ROM_DATA[4] => Mux~2.IN130
ROM_DATA[4] => Mux~3.IN130
ROM_DATA[5] => Mux~0.IN129
ROM_DATA[5] => Mux~1.IN129
ROM_DATA[5] => Mux~2.IN129
ROM_DATA[5] => Mux~3.IN129
ROM_DATA[6] => Mux~0.IN128
ROM_DATA[6] => Mux~1.IN128
ROM_DATA[6] => Mux~2.IN128
ROM_DATA[6] => Mux~3.IN128
ROM_DATA[7] => Mux~0.IN127
ROM_DATA[7] => Mux~1.IN127
ROM_DATA[7] => Mux~2.IN127
ROM_DATA[7] => Mux~3.IN127
ROM_DATA[8] => Mux~0.IN126
ROM_DATA[8] => Mux~1.IN126
ROM_DATA[8] => Mux~2.IN126
ROM_DATA[8] => Mux~3.IN126
ROM_DATA[9] => Mux~0.IN125
ROM_DATA[9] => Mux~1.IN125
ROM_DATA[9] => Mux~2.IN125
ROM_DATA[9] => Mux~3.IN125
ROM_DATA[10] => Mux~0.IN124
ROM_DATA[10] => Mux~1.IN124
ROM_DATA[10] => Mux~2.IN124
ROM_DATA[10] => Mux~3.IN124
ROM_DATA[11] => Mux~0.IN123
ROM_DATA[11] => Mux~1.IN123
ROM_DATA[11] => Mux~2.IN123
ROM_DATA[11] => Mux~3.IN123
ROM_DATA[12] => Mux~0.IN122
ROM_DATA[12] => Mux~1.IN122
ROM_DATA[12] => Mux~2.IN122
ROM_DATA[12] => Mux~3.IN122
ROM_DATA[13] => Mux~0.IN121
ROM_DATA[13] => Mux~1.IN121
ROM_DATA[13] => Mux~2.IN121
ROM_DATA[13] => Mux~3.IN121
ROM_DATA[14] => Mux~0.IN120
ROM_DATA[14] => Mux~1.IN120
ROM_DATA[14] => Mux~2.IN120
ROM_DATA[14] => Mux~3.IN120
ROM_DATA[15] => Mux~0.IN119
ROM_DATA[15] => Mux~1.IN119
ROM_DATA[15] => Mux~2.IN119
ROM_DATA[15] => Mux~3.IN119
ROM_DATA[16] => Mux~0.IN118
ROM_DATA[16] => Mux~1.IN118
ROM_DATA[16] => Mux~2.IN118
ROM_DATA[16] => Mux~3.IN118
ROM_DATA[17] => Mux~0.IN117
ROM_DATA[17] => Mux~1.IN117
ROM_DATA[17] => Mux~2.IN117
ROM_DATA[17] => Mux~3.IN117
ROM_DATA[18] => Mux~0.IN116
ROM_DATA[18] => Mux~1.IN116
ROM_DATA[18] => Mux~2.IN116
ROM_DATA[18] => Mux~3.IN116
ROM_DATA[19] => Mux~0.IN115
ROM_DATA[19] => Mux~1.IN115
ROM_DATA[19] => Mux~2.IN115
ROM_DATA[19] => Mux~3.IN115
ROM_DATA[20] => Mux~0.IN114
ROM_DATA[20] => Mux~1.IN114
ROM_DATA[20] => Mux~2.IN114
ROM_DATA[20] => Mux~3.IN114
ROM_DATA[21] => Mux~0.IN113
ROM_DATA[21] => Mux~1.IN113