songer.map.qmsg

基于FPGA的乐曲硬件演奏电路设计的实现

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" "lpm_decode" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" 67 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/decode_9ie.tdf" "decode_9ie" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/decode_9ie.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "sld_dffex-DFFEX" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "sld_dffex" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "16 " "Info: Ignored 16 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "16 " "Info: Ignored 16 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Speakera:u3\|SpkS Speakera:u3\|\\DelaySpkS:Count2 " "Info: Duplicate register Speakera:u3\|SpkS merged to single register Speakera:u3\|\\DelaySpkS:Count2" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "NoteTabs:u1\|Counter\[0\]~0 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: NoteTabs:u1\|Counter\[0\]~0" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/notetabs.vhd" "" "Counter\[0\]~0" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/notetabs.vhd" 18 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speakera:u3\|\\GenSpkS:Count11\[0\]~0 11 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: Speakera:u3\|\\GenSpkS:Count11\[0\]~0" {  } {  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speakera:u3\|\\DivideCLK:Count4\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: Speakera:u3\|\\DivideCLK:Count4\[0\]~0" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~320 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~320" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "ram_rom_addr_reg\[0\]~320" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 394 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ia7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ia7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ia7 " "Info: Found entity 1: cntr_ia7" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ia7.tdf" "cntr_ia7" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ia7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_7t7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_7t7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_7t7 " "Info: Found entity 1: cntr_7t7" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" "cntr_7t7" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ea7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ea7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ea7 " "Info: Found entity 1: cntr_ea7" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" "cntr_ea7" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v98.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_v98.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v98 " "Info: Found entity 1: cntr_v98" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_v98.tdf" "cntr_v98" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_v98.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "CODE1\[3\] GND " "Warning: Pin CODE1\[3\] stuck at GND" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "249 " "Info: Implemented 249 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "232 " "Info: Implemented 232 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 07 14:09:41 2005 " "Info: Processing ended: Wed Sep 07 14:09:41 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0}  } {  } 0}