songer.fit.qmsg

基于FPGA的乐曲硬件演奏电路设计的实现

{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.604 ns register register " "Info: Estimated most critical path is register to register delay of 3.604 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[0\] 1 REG LAB_X11_Y4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y4; Fanout = 3; REG Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[0\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 425 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.282 ns) + CELL(0.114 ns) 1.396 ns sld_hub:sld_hub_inst\|HUB_TDO~363 2 COMB LAB_X11_Y6 1 " "Info: 2: + IC(1.282 ns) + CELL(0.114 ns) = 1.396 ns; Loc. = LAB_X11_Y6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~363'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.396 ns" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] sld_hub:sld_hub_inst|HUB_TDO~363 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.519 ns) + CELL(0.292 ns) 2.207 ns sld_hub:sld_hub_inst\|HUB_TDO~335 3 COMB LAB_X12_Y6 1 " "Info: 3: + IC(0.519 ns) + CELL(0.292 ns) = 2.207 ns; Loc. = LAB_X12_Y6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~335'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "0.811 ns" { sld_hub:sld_hub_inst|HUB_TDO~363 sld_hub:sld_hub_inst|HUB_TDO~335 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.114 ns) 2.839 ns sld_hub:sld_hub_inst\|HUB_TDO~341 4 COMB LAB_X12_Y6 1 " "Info: 4: + IC(0.518 ns) + CELL(0.114 ns) = 2.839 ns; Loc. = LAB_X12_Y6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~341'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "0.632 ns" { sld_hub:sld_hub_inst|HUB_TDO~335 sld_hub:sld_hub_inst|HUB_TDO~341 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.287 ns) + CELL(0.478 ns) 3.604 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 5 REG LAB_X12_Y6 0 " "Info: 5: + IC(0.287 ns) + CELL(0.478 ns) = 3.604 ns; Loc. = LAB_X12_Y6; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "0.765 ns" { sld_hub:sld_hub_inst|HUB_TDO~341 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.998 ns 27.69 % " "Info: Total cell delay = 0.998 ns ( 27.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.606 ns 72.31 % " "Info: Total interconnect delay = 2.606 ns ( 72.31 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "3.604 ns" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] sld_hub:sld_hub_inst|HUB_TDO~363 sld_hub:sld_hub_inst|HUB_TDO~335 sld_hub:sld_hub_inst|HUB_TDO~341 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Estimated interconnect usage is 2% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode" } } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 505 -1 0 } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[1\] -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[1\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[0\] -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[0\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[2\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[2\] -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[2\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] } "NODE_NAME" } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CODE1\[3\] GND " "Info: Pin CODE1\[3\] has GND driving its datain port" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 6 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CODE1\[3\]" } } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { CODE1[3] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fld" "" "" { CODE1[3] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 07 14:09:54 2005 " "Info: Processing ended: Wed Sep 07 14:09:54 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}