songer.tan.summary

基于FPGA的乐曲硬件演奏电路设计的实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.626 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.740 ns
From           : NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_address_reg7
To             : CODE1[2]
From Clock     : CLK8HZ
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.689 ns
From           : altera_internal_jtag
To             : NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.107 ns
From           : NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_address_reg7
To             : CODE1[1]
From Clock     : CLK8HZ
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 128.17 MHz ( period = 7.802 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : sld_hub:sld_hub_inst|HUB_TDO~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLK12MHZ'
Slack          : N/A
Required Time  : None
Actual Time    : 187.34 MHz ( period = 5.338 ns )
From           : Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4]
To             : Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[0]
From Clock     : CLK12MHZ
To Clock       : CLK12MHZ
Failed Paths   : 0

Type           : Clock Setup: 'CLK8HZ'
Slack          : N/A
Required Time  : None
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg0
To             : NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg0
From Clock     : CLK8HZ
To Clock       : CLK8HZ
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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