ledrun.v

来自「用fpga实现isp接口的源码」· Verilog 代码 · 共 54 行

module LEDRun (reset,gclk,cpusel,cpurd,cpuwr,addr,indata,outdata,leddata);

input reset;
input [11:0]addr;
input [7:0]indata;
input gclk;
input cpusel;
input cpurd;
input cpuwr;

output [7:0]outdata;		//用于给cpu的数据输出
output [3:0] leddata;

reg [7:0]outdata;
reg [7:0]ledtemp;
reg [3:0] leddata;
reg WSuccess;
reg leden;

always @(negedge cpurd)
	if(cpusel==0)
		case(addr)
//			12'b110000000000: outdata[7:0]=ledtemp[7:0];
			12'b000000000000: outdata[7:0]=ledtemp[7:0];
		endcase

always @(posedge cpuwr)
if(~reset)
	ledtemp=8'b11111111;
else	
	if(cpusel==0)
		case(addr)
			12'b000000000000:	
				begin
					ledtemp=indata;
					WSuccess=~WSuccess;	
				end		
		endcase	


always @(posedge gclk)
if(~reset)
	leddata=4'b1111;
else
	begin
		if (leden==~WSuccess)
			begin
				leddata[3:0]=ledtemp[3:0];
				leden=WSuccess;
			end
		else
			leddata=leddata;			
	end
endmodule