test.tan.qmsg

用fpga实现isp接口的源码

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "GCLK 35 " "Warning: Circuit may not operate. Detected 35 non-operational path(s) clocked by clock \"GCLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "SPI:inst\|spiprocess:inst21\|ReceiveData\[3\] SPI:inst\|RAM7:inst10\|altsyncram:altsyncram_component\|altsyncram_jam1:auto_generated\|ram_block1a7~porta_datain_reg4 GCLK 3.368 ns " "Info: Found hold time violation between source  pin or register \"SPI:inst\|spiprocess:inst21\|ReceiveData\[3\]\" and destination pin or register \"SPI:inst\|RAM7:inst10\|altsyncram:altsyncram_component\|altsyncram_jam1:auto_generated\|ram_block1a7~porta_datain_reg4\" for clock \"GCLK\" (Hold time is 3.368 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.323 ns + Largest " "Info: + Largest clock skew is 5.323 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK destination 8.091 ns + Longest memory " "Info: + Longest clock path from clock \"GCLK\" to destination memory is 8.091 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns GCLK 1 CLK PIN_16 109 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 109; CLK Node = 'GCLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GCLK } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 368 312 480 384 "GCLK" "" } { 360 480 592 376 "GCLK" "" } { 552 424 560 568 "GCLK" "" } { 456 800 928 472 "GCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.935 ns) 2.992 ns SPI:inst\|spiprocess:inst21\|ReceiveCLK 2 REG LC_X6_Y9_N3 27 " "Info: 2: + IC(0.588 ns) + CELL(0.935 ns) = 2.992 ns; Loc. = LC_X6_Y9_N3; Fanout = 27; REG Node = 'SPI:inst\|spiprocess:inst21\|ReceiveCLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.523 ns" { GCLK SPI:inst|spiprocess:inst21|ReceiveCLK } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.377 ns) + CELL(0.722 ns) 8.091 ns SPI:inst\|RAM7:inst10\|altsyncram:altsyncram_component\|altsyncram_jam1:auto_generated\|ram_block1a7~porta_datain_reg4 3 MEM M4K_X13_Y9 1 " "Info: 3: + IC(4.377 ns) + CELL(0.722 ns) = 8.091 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'SPI:inst\|RAM7:inst10\|altsyncram:altsyncram_component\|altsyncram_jam1:auto_generated\|ram_block1a7~porta_datain_reg4'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.099 ns" { SPI:inst|spiprocess:inst21|ReceiveCLK SPI:inst|RAM7:inst10|altsyncram:altsyncram_component|altsyncram_jam1:auto_generated|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "db/altsyncram_jam1.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/altsyncram_jam1.tdf" 272 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 38.64 % ) " "Info: Total cell delay = 3.126 ns ( 38.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.965 ns ( 61.36 % ) " "Info: Total interconnect delay = 4.965 ns ( 61.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.091 ns" { GCLK SPI:inst|spiprocess:inst21|ReceiveCLK SPI:inst|RAM7:inst10|altsyncram:altsyncram_component|altsyncram_jam1:auto_generated|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.091 ns" { GCLK GCLK~out0 SPI:inst|spiprocess:inst21|ReceiveCLK SPI:inst|RAM7:inst10|altsyncram:altsyncram_component|altsyncram_jam1:auto_generated|ram_block1a7~porta_datain_reg4 } { 0.000ns 0.000ns 0.588ns 4.377ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK source 2.768 ns - Shortest register " "Info: - Shortest clock path from clock \"GCLK\" to source register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns GCLK 1 CLK PIN_16 109 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 109; CLK Node = 'GCLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GCLK } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 368 312 480 384 "GCLK" "" } { 360 480 592 376 "GCLK" "" } { 552 424 560 568 "GCLK" "" } { 456 800 928 472