📄 test.tan.qmsg

📁 用fpga实现isp接口的源码
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "WR register register SPI:inst\|spiprocess:inst21\|CE SPI:inst\|spiprocess:inst21\|CE 275.03 MHz Internal " "Info: Clock \"WR\" Internal fmax is restricted to 275.03 MHz between source register \"SPI:inst\|spiprocess:inst21\|CE\" and destination register \"SPI:inst\|spiprocess:inst21\|CE\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.402 ns + Longest register register " "Info: + Longest register to register delay is 1.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SPI:inst\|spiprocess:inst21\|CE 1 REG LC_X11_Y11_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y11_N0; Fanout = 4; REG Node = 'SPI:inst\|spiprocess:inst21\|CE'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.114 ns) 0.656 ns SPI:inst\|spiprocess:inst21\|CE~155 2 COMB LC_X11_Y11_N5 1 " "Info: 2: + IC(0.542 ns) + CELL(0.114 ns) = 0.656 ns; Loc. = LC_X11_Y11_N5; Fanout = 1; COMB Node = 'SPI:inst\|spiprocess:inst21\|CE~155'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.656 ns" { SPI:inst|spiprocess:inst21|CE SPI:inst|spiprocess:inst21|CE~155 } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.309 ns) 1.402 ns SPI:inst\|spiprocess:inst21\|CE 3 REG LC_X11_Y11_N0 4 " "Info: 3: + IC(0.437 ns) + CELL(0.309 ns) = 1.402 ns; Loc. = LC_X11_Y11_N0; Fanout = 4; REG Node = 'SPI:inst\|spiprocess:inst21\|CE'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.746 ns" { SPI:inst|spiprocess:inst21|CE~155 SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.423 ns ( 30.17 % ) " "Info: Total cell delay = 0.423 ns ( 30.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.979 ns ( 69.83 % ) " "Info: Total interconnect delay = 0.979 ns ( 69.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.402 ns" { SPI:inst|spiprocess:inst21|CE SPI:inst|spiprocess:inst21|CE~155 SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.402 ns" { SPI:inst|spiprocess:inst21|CE SPI:inst|spiprocess:inst21|CE~155 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.542ns 0.437ns } { 0.000ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 6.798 ns + Shortest register " "Info: + Shortest clock path from clock \"WR\" to destination register is 6.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns WR 1 CLK PIN_107 520 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_107; Fanout = 520; CLK Node = 'WR'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 416 312 480 432 "WR" "" } { 408 480 592 424 "WR" "" } { 584 424 560 600 "WR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.618 ns) + CELL(0.711 ns) 6.798 ns SPI:inst\|spiprocess:inst21\|CE 2 REG LC_X11_Y11_N0 4 " "Info: 2: + IC(4.618 ns) + CELL(0.711 ns) = 6.798 ns; Loc. = LC_X11_Y11_N0; Fanout = 4; REG Node = 'SPI:inst\|spiprocess:inst21\|CE'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.329 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 32.07 % ) " "Info: Total cell delay = 2.180 ns ( 32.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.618 ns ( 67.93 % ) " "Info: Total interconnect delay = 4.618 ns ( 67.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.798 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.798 ns" { WR WR~out0 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.000ns 4.618ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR source 6.798 ns - Longest register " "Info: - Longest clock path from clock \"WR\" to source register is 6.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns WR 1 CLK PIN_107 520 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_107; Fanout = 520; CLK Node = 'WR'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 416 312 480 432 "WR" "" } { 408 480 592 424 "WR" "" } { 584 424 560 600 "WR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.618 ns) + CELL(0.711 ns) 6.798 ns SPI:inst\|spiprocess:inst21\|CE 2 REG LC_X11_Y11_N0 4 " "Info: 2: + IC(4.618 ns) + CELL(0.711 ns) = 6.798 ns; Loc. = LC_X11_Y11_N0; Fanout = 4; REG Node = 'SPI:inst\|spiprocess:inst21\|CE'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.329 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 32.07 % ) " "Info: Total cell delay = 2.180 ns ( 32.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.618 ns ( 67.93 % ) " "Info: Total interconnect delay = 4.618 ns ( 67.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.798 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.798 ns" { WR WR~out0 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.000ns 4.618ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.798 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.798 ns" { WR WR~out0 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.000ns 4.618ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.798 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.798 ns" { WR WR~out0 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.000ns 4.618ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.402 ns" { SPI:inst|spiprocess:inst21|CE SPI:inst|spiprocess:inst21|CE~155 SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.402 ns" { SPI:inst|spiprocess:inst21|CE SPI:inst|spiprocess:inst21|CE~155 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.542ns 0.437ns } { 0.000ns 0.114ns 0.309ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.798 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.798 ns" { WR WR~out0 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.000ns 4.618ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.798 ns" { WR SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.798 ns" { WR WR~out0 SPI:inst|spiprocess:inst21|CE } { 0.000ns 0.000ns 4.618ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|spiprocess:inst21|CE } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { SPI:inst|spiprocess:inst21|CE } {  } {  } } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 26 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "RFirq register register SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2 SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2 275.03 MHz Internal " "Info: Clock \"RFirq\" Internal fmax is restricted to 275.03 MHz between source register \"SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2\" and destination register \"SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.892 ns + Longest register register " "Info: + Longest register to register delay is 0.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2 1 REG LC_X4_Y10_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y10_N5; Fanout = 6; REG Node = 'SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.583 ns) + CELL(0.309 ns) 0.892 ns SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2 2 REG LC_X4_Y10_N5 6 " "Info: 2: + IC(0.583 ns) + CELL(0.309 ns) = 0.892 ns; Loc. = LC_X4_Y10_N5; Fanout = 6; REG Node = 'SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 34.64 % ) " "Info: Total cell delay = 0.309 ns ( 34.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.583 ns ( 65.36 % ) " "Info: Total interconnect delay = 0.583 ns ( 65.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.892 ns" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.583ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RFirq destination 7.224 ns + Shortest register " "Info: + Shortest clock path from clock \"RFirq\" to destination register is 7.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns RFirq 1 CLK PIN_10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'RFirq'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RFirq } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 688 256 424 704 "RFirq" "" } { 680 424 560 696 "RFirq" "" } { 824 840 920 840 "RFirq" "" } { 976 648 792 992 "RFirq" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.044 ns) + CELL(0.711 ns) 7.224 ns SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2 2 REG LC_X4_Y10_N5 6 " "Info: 2: + IC(5.044 ns) + CELL(0.711 ns) = 7.224 ns; Loc. = LC_X4_Y10_N5; Fanout = 6; REG Node = 'SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.755 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 30.18 % ) " "Info: Total cell delay = 2.180 ns ( 30.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.044 ns ( 69.82 % ) " "Info: Total interconnect delay = 5.044 ns ( 69.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.224 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.224 ns" { RFirq RFirq~out0 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.000ns 5.044ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RFirq source 7.224 ns - Longest register " "Info: - Longest clock path from clock \"RFirq\" to source register is 7.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns RFirq 1 CLK PIN_10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'RFirq'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RFirq } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 688 256 424 704 "RFirq" "" } { 680 424 560 696 "RFirq" "" } { 824 840 920 840 "RFirq" "" } { 976 648 792 992 "RFirq" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.044 ns) + CELL(0.711 ns) 7.224 ns SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2 2 REG LC_X4_Y10_N5 6 " "Info: 2: + IC(5.044 ns) + CELL(0.711 ns) = 7.224 ns; Loc. = LC_X4_Y10_N5; Fanout = 6; REG Node = 'SPI:inst\|spiprocess:inst21\|T_ReceivesomeData2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.755 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 30.18 % ) " "Info: Total cell delay = 2.180 ns ( 30.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.044 ns ( 69.82 % ) " "Info: Total interconnect delay = 5.044 ns ( 69.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.224 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.224 ns" { RFirq RFirq~out0 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.000ns 5.044ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.224 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.224 ns" { RFirq RFirq~out0 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.000ns 5.044ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.224 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.224 ns" { RFirq RFirq~out0 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.000ns 5.044ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 78 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 78 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.892 ns" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.583ns } { 0.000ns 0.309ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.224 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.224 ns" { RFirq RFirq~out0 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.000ns 5.044ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.224 ns" { RFirq SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.224 ns" { RFirq RFirq~out0 SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } { 0.000ns 0.000ns 5.044ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { SPI:inst|spiprocess:inst21|T_ReceivesomeData2 } {  } {  } } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 78 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "RD register register SPI:inst\|spiprocess:inst21\|outdata\[0\] SPI:inst\|spiprocess:inst21\|outdata\[0\] 275.03 MHz Internal " "Info: Clock \"RD\" Internal fmax is restricted to 275.03 MHz between source register \"SPI:inst\|spiprocess:inst21\|outdata\[0\]\" and destination register \"SPI:inst\|spiprocess:inst21\|outdata\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.143 ns + Longest register register " "Info: + Longest register to register delay is 1.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SPI:inst\|spiprocess:inst21\|outdata\[0\] 1 REG LC_X10_Y6_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N3; Fanout = 2; REG Node = 'SPI:inst\|spiprocess:inst21\|outdata\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.114 ns) 0.652 ns SPI:inst\|spiprocess:inst21\|Selector7~115 2 COMB LC_X10_Y6_N2 1 " "Info: 2: + IC(0.538 ns) + CELL(0.114 ns) = 0.652 ns; Loc. = LC_X10_Y6_N2; Fanout = 1; COMB Node = 'SPI:inst\|spiprocess:inst21\|Selector7~115'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.652 ns" { SPI:inst|spiprocess:inst21|outdata[0] SPI:inst|spiprocess:inst21|Selector7~115 } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 1.143 ns SPI:inst\|spiprocess:inst21\|outdata\[0\] 3 REG LC_X10_Y6_N3 2 " "Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 1.143 ns; Loc. = LC_X10_Y6_N3; Fanout = 2; REG Node = 'SPI:inst\|spiprocess:inst21\|outdata\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.491 ns" { SPI:inst|spiprocess:inst21|Selector7~115 SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.423 ns ( 37.01 % ) " "Info: Total cell delay = 0.423 ns ( 37.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.720 ns ( 62.99 % ) " "Info: Total interconnect delay = 0.720 ns ( 62.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.143 ns" { SPI:inst|spiprocess:inst21|outdata[0] SPI:inst|spiprocess:inst21|Selector7~115 SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.143 ns" { SPI:inst|spiprocess:inst21|outdata[0] SPI:inst|spiprocess:inst21|Selector7~115 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.538ns 0.182ns } { 0.000ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RD destination 6.776 ns + Shortest register " "Info: + Shortest clock path from clock \"RD\" to destination register is 6.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns RD 1 CLK PIN_108 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_108; Fanout = 16; CLK Node = 'RD'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 400 312 480 416 "RD" "" } { 392 480 592 408 "RD" "" } { 208 456 560 224 "RD" "" } { 632 424 560 648 "RD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.596 ns) + CELL(0.711 ns) 6.776 ns SPI:inst\|spiprocess:inst21\|outdata\[0\] 2 REG LC_X10_Y6_N3 2 " "Info: 2: + IC(4.596 ns) + CELL(0.711 ns) = 6.776 ns; Loc. = LC_X10_Y6_N3; Fanout = 2; REG Node = 'SPI:inst\|spiprocess:inst21\|outdata\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.307 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 32.17 % ) " "Info: Total cell delay = 2.180 ns ( 32.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.596 ns ( 67.83 % ) " "Info: Total interconnect delay = 4.596 ns ( 67.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.776 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.776 ns" { RD RD~out0 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RD source 6.776 ns - Longest register " "Info: - Longest clock path from clock \"RD\" to source register is 6.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns RD 1 CLK PIN_108 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_108; Fanout = 16; CLK Node = 'RD'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 400 312 480 416 "RD" "" } { 392 480 592 408 "RD" "" } { 208 456 560 224 "RD" "" } { 632 424 560 648 "RD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.596 ns) + CELL(0.711 ns) 6.776 ns SPI:inst\|spiprocess:inst21\|outdata\[0\] 2 REG LC_X10_Y6_N3 2 " "Info: 2: + IC(4.596 ns) + CELL(0.711 ns) = 6.776 ns; Loc. = LC_X10_Y6_N3; Fanout = 2; REG Node = 'SPI:inst\|spiprocess:inst21\|outdata\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.307 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 32.17 % ) " "Info: Total cell delay = 2.180 ns ( 32.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.596 ns ( 67.83 % ) " "Info: Total interconnect delay = 4.596 ns ( 67.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.776 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.776 ns" { RD RD~out0 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.776 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.776 ns" { RD RD~out0 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.776 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.776 ns" { RD RD~out0 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 98 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 98 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.143 ns" { SPI:inst|spiprocess:inst21|outdata[0] SPI:inst|spiprocess:inst21|Selector7~115 SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.143 ns" { SPI:inst|spiprocess:inst21|outdata[0] SPI:inst|spiprocess:inst21|Selector7~115 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.538ns 0.182ns } { 0.000ns 0.114ns 0.309ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.776 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.776 ns" { RD RD~out0 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.776 ns" { RD SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.776 ns" { RD RD~out0 SPI:inst|spiprocess:inst21|outdata[0] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|spiprocess:inst21|outdata[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { SPI:inst|spiprocess:inst21|outdata[0] } {  } {  } } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 98 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
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