test.tan.qmsg

用fpga实现isp接口的源码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "GCLK " "Info: Assuming node \"GCLK\" is an undefined clock" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 368 312 480 384 "GCLK" "" } { 360 480 592 376 "GCLK" "" } { 552 424 560 568 "GCLK" "" } { 456 800 928 472 "GCLK" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 416 312 480 432 "WR" "" } { 408 480 592 424 "WR" "" } { 584 424 560 600 "WR" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "RFirq " "Info: Assuming node \"RFirq\" is an undefined clock" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 688 256 424 704 "RFirq" "" } { 680 424 560 696 "RFirq" "" } { 824 840 920 840 "RFirq" "" } { 976 648 792 992 "RFirq" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "RFirq" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "RD " "Info: Assuming node \"RD\" is an undefined clock" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 400 312 480 416 "RD" "" } { 392 480 592 408 "RD" "" } { 208 456 560 224 "RD" "" } { 632 424 560 648 "RD" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "RD" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "SPI:inst\|spiprocess:inst21\|ReceiveCLK " "Info: Detected ripple clock \"SPI:inst\|spiprocess:inst21\|ReceiveCLK\" as buffer" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 24 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SPI:inst\|spiprocess:inst21\|ReceiveCLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "SPI:inst\|spiprocess:inst21\|SendramCLK " "Info: Detected ripple clock \"SPI:inst\|spiprocess:inst21\|SendramCLK\" as buffer" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 23 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SPI:inst\|spiprocess:inst21\|SendramCLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "GCLK register SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[0\] register SPI:inst\|spiprocess:inst21\|ramsendtemp\[1\] 72.97 MHz 13.705 ns Internal " "Info: Clock \"GCLK\" has Internal fmax of 72.97 MHz between source register \"SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[0\]\" and destination register \"SPI:inst\|spiprocess:inst21\|ramsendtemp\[1\]\" (period= 13.705 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.986 ns + Longest register register " "Info: + Longest register to register delay is 8.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[0\] 1 REG LC_X17_Y8_N6 200 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y8_N6; Fanout = 200; REG Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } "NODE_NAME" } } { "altdpram.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altdpram.tdf" 406 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.456 ns) + CELL(0.442 ns) 1.898 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5627 2 COMB LC_X18_Y12_N3 1 " "Info: 2: + IC(1.456 ns) + CELL(0.442 ns) = 1.898 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5627'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.898 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5627 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.442 ns) 3.605 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5628 3 COMB LC_X17_Y10_N2 1 " "Info: 3: + IC(1.265 ns) + CELL(0.442 ns) = 3.605 ns; Loc. = LC_X17_Y10_N2; Fanout = 1; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5628'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.707 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5627 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.292 ns) 4.339 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5629 4 COMB LC_X17_Y10_N4 1 " "Info: 4: + IC(0.442 ns) + CELL(0.292 ns) = 4.339 ns; Loc. = LC_X17_Y10_N4; Fanout = 1; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5629'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.734 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.807 ns) + CELL(0.590 ns) 6.736 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5630 5 COMB LC_X12_Y8_N0 2 " "Info: 5: + IC(1.807 ns) + CELL(0.590 ns) = 6.736 ns; Loc. = LC_X12_Y8_N0; Fanout = 2; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5630'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.397 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.114 ns) 8.111 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5631 6 COMB LC_X11_Y7_N5 3 " "Info: 6: + IC(1.261 ns) + CELL(0.114 ns) = 8.111 ns; Loc. = LC_X11_Y7_N5; Fanout = 3; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[1\]~5631'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.375 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.115 ns) 8.986 ns SPI:inst\|spiprocess:inst21\|ramsendtemp\[1\] 7 REG LC_X10_Y7_N7 1 " "Info: 7: + IC(0.760 ns) + CELL(0.115 ns) = 8.986 ns; Loc. = LC_X10_Y7_N7; Fanout = 1; REG Node = 'SPI:inst\|spiprocess:inst21\|ramsendtemp\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.875 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 SPI:inst|spiprocess:inst21|ramsendtemp[1] } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 1493 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.995 ns ( 22.20 % ) " "Info: Total cell delay = 1.995 ns ( 22.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.991 ns ( 77.80 % ) " "Info: Total interconnect delay = 6.991 ns ( 77.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.986 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5627 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 SPI:inst|spiprocess:inst21|ramsendtemp[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.986 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5627 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 SPI:inst|spiprocess:inst21|ramsendtemp[1] } { 0.000ns 1.456ns 1.265ns 0.442ns 1.807ns 1.261ns 0.760ns } { 0.000ns 0.442ns 0.442ns 0.292ns 0.590ns 0.114ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.458 ns - Smallest " "Info: - Smallest clock skew is -4.458 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock \"GCLK\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns GCLK 1 CLK PIN_16 109 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 109; CLK Node = 'GCLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GCLK } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 368 312 480 384 "GCLK" "" } { 360 480 592 376 "GCLK" "" } { 552 424 560 568 "GCLK" "" } { 456 800 928 472 "GCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns SPI:inst\|spiprocess:inst21\|ramsendtemp\[1\] 2 REG LC_X10_Y7_N7 1 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X10_Y7_N7; Fanout = 1; REG Node = 'SPI:inst\|spiprocess:inst21\|ramsendtemp\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { GCLK SPI:inst|spiprocess:inst21|ramsendtemp[1] } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 1493 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { GCLK SPI:inst|spiprocess:inst21|ramsendtemp[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { GCLK GCLK~out0 SPI:inst|spiprocess:inst21|ramsendtemp[1] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK source 7.198 ns - Longest register " "Info: - Longest clock path from clock \"GCLK\" to source register is 7.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns GCLK 1 CLK PIN_16 109 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 109; CLK Node = 'GCLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GCLK } "NODE_NAME" } } { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 368 312 480 384 "GCLK" "" } { 360 480 592 376 "GCLK" "" } { 552 424 560 568 "GCLK" "" } { 456 800 928 472 "GCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns SPI:inst\|spiprocess:inst21\|SendramCLK 2 REG LC_X8_Y6_N7 17 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N7; Fanout = 17; REG Node = 'SPI:inst\|spiprocess:inst21\|SendramCLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { GCLK SPI:inst|spiprocess:inst21|SendramCLK } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.523 ns) + CELL(0.711 ns) 7.198 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[0\] 3 REG LC_X17_Y8_N6 200 " "Info: 3: + IC(3.523 ns) + CELL(0.711 ns) = 7.198 ns; Loc. = LC_X17_Y8_N6; Fanout = 200; REG Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.234 ns" { SPI:inst|spiprocess:inst21|SendramCLK SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } "NODE_NAME" } } { "altdpram.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altdpram.tdf" 406 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.28 % ) " "Info: Total cell delay = 3.115 ns ( 43.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.083 ns ( 56.72 % ) " "Info: Total interconnect delay = 4.083 ns ( 56.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.198 ns" { GCLK SPI:inst|spiprocess:inst21|SendramCLK SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.198 ns" { GCLK GCLK~out0 SPI:inst|spiprocess:inst21|SendramCLK SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } { 0.000ns 0.000ns 0.560ns 3.523ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { GCLK SPI:inst|spiprocess:inst21|ramsendtemp[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { GCLK GCLK~out0 SPI:inst|spiprocess:inst21|ramsendtemp[1] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.198 ns" { GCLK SPI:inst|spiprocess:inst21|SendramCLK SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.198 ns" { GCLK GCLK~out0 SPI:inst|spiprocess:inst21|SendramCLK SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } { 0.000ns 0.000ns 0.560ns 3.523ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "altdpram.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altdpram.tdf" 406 12 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 1493 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.986 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5627 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 SPI:inst|spiprocess:inst21|ramsendtemp[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.986 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5627 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 SPI:inst|spiprocess:inst21|ramsendtemp[1] } { 0.000ns 1.456ns 1.265ns 0.442ns 1.807ns 1.261ns 0.760ns } { 0.000ns 0.442ns 0.442ns 0.292ns 0.590ns 0.114ns 0.115ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { GCLK SPI:inst|spiprocess:inst21|ramsendtemp[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { GCLK GCLK~out0 SPI:inst|spiprocess:inst21|ramsendtemp[1] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.198 ns" { GCLK SPI:inst|spiprocess:inst21|SendramCLK SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.198 ns" { GCLK GCLK~out0 SPI:inst|spiprocess:inst21|SendramCLK SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0] } { 0.000ns 0.000ns 0.560ns 3.523ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}