test.hif

用fpga实现isp接口的源码

Version 6.0 Build 178 04/27/2006 SJ Web Edition
35
1731
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
RAM7
# storage
db|TEST.(3).cnf
db|TEST.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RAM7.v
28ae782018d69390476850d6aaab4b3
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SPI:inst|RAM7:inst10
}
# end
# entity
altsyncram
# storage
db|TEST.(4).cnf
db|TEST.(4).cnf
# case_insensitive
# source_file
e:|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
6
PARAMETER_DEC
USR
NUMWORDS_A
64
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
6
PARAMETER_DEC
USR
NUMWORDS_B
64
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_jam1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_b
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
data_b
-1
2
clocken1
-1
2
clocken0
-1
2
byteena_b
-1
2
byteena_a
-1
2
}
# include_file {
e:|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
e:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
e:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
e:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
e:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
e:|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
e:|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
e:|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
e:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
SPI:inst|RAM7:inst10|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_jam1
# storage
db|TEST.(5).cnf
db|TEST.(5).cnf
# case_insensitive
# source_file
db|altsyncram_jam1.tdf
1c5a42583c85e2c83f253eb6ff679a60
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
SPI:inst|RAM7:inst10|altsyncram:altsyncram_component|altsyncram_jam1:auto_generated
}
# end
# entity
MUX7
# storage
db|TEST.(7).cnf
db|TEST.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MUX7.v
c73f24b64314dc599037c824d82af491
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SPI:inst|MUX7:inst16
}
# end
# entity
lpm_mux
# storage
db|TEST.(8).cnf
db|TEST.(8).cnf
# case_insensitive
# source_file
e:|altera|quartus60|libraries|megafunctions|lpm_mux.tdf
9bf66e437b499c0f0b81c977a5a50
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
8
PARAMETER_DEC
USR
LPM_SIZE
2
PARAMETER_DEC
USR
LPM_WIDTHS
1
PARAMETER_DEC
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_afc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
sel
-1
3
result
-1
3
data
-1
3
}
# include_file {
e:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
e:|altera|quartus60|libraries|megafunctions|muxlut.inc
f172666ca13e5e31e17e3f6cb35af52
e:|altera|quartus60|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
e:|altera|quartus60|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
}
# hierarchies {
SPI:inst|MUX7:inst16|lpm_mux:lpm_mux_component
}
# end
# entity
mux_afc
# storage
db|TEST.(9).cnf
db|TEST.(9).cnf
# case_insensitive
# source_file
db|mux_afc.tdf
3a33b3b5ce339815e45aa85c346418f
6
# used_port {
sel0
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
SPI:inst|MUX7:inst16|lpm_mux:lpm_mux_component|mux_afc:auto_generated
}
# end
# entity
tritest8
# storage
db|TEST.(12).cnf
db|TEST.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
tritest8.v
5cb83820e1ede05afee10309d2e97cf
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
INTERFACE:inst1|tritest8:inst
}
# end
# entity
lpm_bustri
# storage
db|TEST.(13).cnf
db|TEST.(13).cnf
# case_insensitive
# source_file
e:|altera|quartus60|libraries|megafunctions|lpm_bustri.tdf
60e8a17342b6ea1759f58e54d051d686
6
# user_parameter {
LPM_WIDTH
8
PARAMETER_DEC
USR
}
# used_port {
tridata
-1
3
result
-1
3
enabletr
-1
3
enabledt
-1
3
data
-1
3
}
# hierarchies {
INTERFACE:inst1|tritest8:inst|lpm_bustri:lpm_bustri_component
}
# end
# entity
BUS_S
# storage
db|TEST.(14).cnf
db|TEST.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
BUS_S.v
1aff784aa5143114aa149da289d81e9c
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
BUS_S:inst2
}
# end
# entity
lpm_bustri
# storage
db|TEST.(15).cnf
db|TEST.(15).cnf
# case_insensitive
# source_file
e:|altera|quartus60|libraries|megafunctions|lpm_bustri.tdf
60e8a17342b6ea1759f58e54d051d686
6
# user_parameter {
LPM_WIDTH
8
PARAMETER_DEC
USR
}
# used_port {
tridata
-1
3
enabledt
-1
3
data
-1
3
}
# hierarchies {
BUS_S:inst2|lpm_bustri:lpm_bustri_component
}
# end
# entity
LEDRun
# storage
db|TEST.(16).cnf
db|TEST.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LEDRun.v
92a6bb563ddbe280d311f7d57e3cdde3
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
counter25
# storage
db|TEST.(17).cnf
db|TEST.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
counter25.v
df1acf9cd7abf1372c4353224905b
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
counter25:inst5
}
# end
# entity
lpm_counter
# storage
db|TEST.(18).cnf
db|TEST.(18).cnf
# case_insensitive
# source_file
e:|altera|quartus60|libraries|megafunctions|lpm_counter.tdf
9ee47257a6b8b166152317b4e89afa
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
25
PARAMETER_DEC
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_dth
PARAMETER_UNKNOWN
USR
}
# used_port {
sclr
-1
3
q
-1
3
clock
-1
3
sset
-1
1
sload
-1
1
data
-1
1
aset
-1
1
aload
-1
1
aclr
-1
1
updown
-1
2
cnt_en
-1
2
clk_en
-1
2
cin
-1
2
}
# include_file {
e:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
e:|altera|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
e:|altera|quartus60|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
e:|altera|quartus60|libraries|megafunctions|cmpconst.inc
e61874547688138e6fc0b49ff8760
e:|altera|quartus60|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
e:|altera|quartus60|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
e:|altera|quartus60|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
e:|altera|quartus60|libraries|megafunctions|alt_synch_counter.inc
e64d362a7450ad9895aa7e1e5dc2b42a
e:|altera|quartus60|libraries|megafunctions|alt_synch_counter_f.inc
88e2e3ac71decf106c8d913bf441832f
e:|altera|quartus60|libraries|megafunctions|alt_counter_f10ke.inc
d8a92a43831e9df2804dcf9a927e20
e:|altera|quartus60|libraries|megafunctions|alt_counter_stratix.inc
587bf41cd15486161ec3eb5a1fef4c2
}
# hierarchies {
counter25:inst5|lpm_counter:lpm_counter_component
}
# end
# entity
cntr_dth
# storage
db|TEST.(19).cnf
db|TEST.(19).cnf
# case_insensitive
# source_file
db|cntr_dth.tdf
3d7bef4dede830a1454241341fe53233
6
# used_port {
sclr
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# hierarchies {
counter25:inst5|lpm_counter:lpm_counter_component|cntr_dth:auto_generated
}
# end
# entity
INTERFACE
# storage
db|TEST.(11).cnf
db|TEST.(11).cnf
# case_insensitive
# source_file
INTERFACE.bdf
8767be7ab7bec9e5224ed20da75ba
24
# hierarchies {
INTERFACE:inst1
}
# end
# entity
RAM_WR
# storage
db|TEST.(6).cnf
db|TEST.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RAM_WR.v
ccc7d1b6e6b88db3b6556e3737828dc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SPI:inst|RAM_WR:inst
}
# end
# entity
RAM_RD
# storage
db|TEST.(10).cnf
db|TEST.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RAM_RD.v
9563be963abfcd2ff7181ba859135f21
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SPI:inst|RAM_RD:inst11
}
# end
# entity
RAM_TEST
# storage
db|TEST.(20).cnf
db|TEST.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RAM_TEST.v
e027b7576a951edbfcc4776ed4c65ec4
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SPI:inst|RAM_TEST:inst2
}
# end
# entity
altdpram
# storage
db|TEST.(21).cnf
db|TEST.(21).cnf
# case_insensitive
# source_file
e:|altera|quartus60|libraries|megafunctions|altdpram.tdf
77a3b19326a7fb3784089553ecd229
6
# user_parameter {
WIDTH
8
PARAMETER_DEC
USR
WIDTHAD
6
PARAMETER_DEC
USR
NUMWORDS
64
PARAMETER_UNKNOWN
DEF
FILE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
-1
3
wraddress
-1
3
rden
-1
3
rdaddress
-1
3
q
-1
3
outclock
-1
3
inclock
-1
3
data
-1
3
aclr
-1
1
outclocken
-1
2
inclocken
-1
2
}
# include_file {
e:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
e:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
e:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
e:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
e:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
e:|altera|quartus60|libraries|megafunctions|a_hdffe.inc
6e1dd1dda0dcf1122cd2b84d66c10b3
e:|altera|quartus60|libraries|others|maxplus2|memmodes.inc
44d4551a35f349f0dbacaf799d39950
e:|altera|quartus60|libraries|megafunctions|alt_le_rden_reg.inc
7591066e9fa6e1ee16e5ba18b60506f
}
# hierarchies {
SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component
}
# end
# entity
lpm_mux
# storage
db|TEST.(22).cnf
db|TEST.(22).cnf
# case_insensitive
# source_file
e:|altera|quartus60|libraries|megafunctions|lpm_mux.tdf
9bf66e437b499c0f0b81c977a5a50
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_SIZE
64
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
6
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_7hc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
sel5
-1
3
sel4
-1
3
sel3
-1
3
sel2
-1
3
sel1
-1
3
sel0
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
data9_7
-1
3
data9_6
-1
3
data9_5
-1
3
data9_4
-1
3
data9_3
-1
3
data9_2
-1
3
data9_1
-1
3
data9_0
-1
3
data8_7
-1
3
data8_6
-1
3
data8_5
-1
3
data8_4
-1
3
data8_3
-1
3
data8_2
-1
3
data8_1
-1
3
data8_0
-1
3
data7_7
-1
3
data7_6
-1
3
data7_5
-1
3
data7_4
-1
3
data7_3
-1
3
data7_2
-1
3
data7_1
-1
3
data7_0
-1
3
data6_7
-1
3
data6_6
-1
3
data6_5
-1
3
data6_4
-1
3
data6_3
-1
3
data6_2
-1
3
data6_1
-1
3
data6_0
-1
3
data63_7
-1
3
data63_6
-1
3
data63_5
-1
3
data63_4
-1
3
data63_3
-1
3
data63_2
-1
3
data63_1
-1
3
data63_0
-1
3
data62_7
-1
3
data62_6
-1
3
data62_5
-1
3
data62_4
-1
3
data62_3
-1
3
data62_2
-1
3
data62_1
-1
3
data62_0
-1
3
data61_7
-1
3
data61_6
-1
3
data61_5
-1
3
data61_4
-1
3
data61_3
-1
3
data61_2
-1
3
data61_1
-1
3
data61_0
-1
3
data60_7
-1
3
data60_6
-1
3
data60_5
-1
3
data60_4
-1
3
data60_3
-1
3
data60_2
-1
3
data60_1
-1
3
data60_0
-1
3
data5_7
-1
3
data5_6
-1
3
data5_5
-1
3
data5_4
-1
3
data5_3
-1
3
data5_2
-1
3
data5_1
-1
3
data5_0
-1
3
data59_7
-1
3
data59_6
-1
3
data59_5
-1
3
data59_4
-1
3
data59_3
-1
3
data59_2
-1
3
data59_1
-1
3
data59_0
-1
3
data58_7
-1
3
data58_6
-1
3
data58_5
-1
3
data58_4
-1
3
data58_3
-1
3
data58_2
-1
3
data58_1
-1
3
data58_0
-1
3
data57_7
-1
3
data57_6
-1
3
data57_5
-1
3
data57_4
-1
3
data57_3
-1
3
data57_2
-1
3
data57_1
-1
3
data57_0
-1
3
data56_7
-1
3
data56_6
-1
3
data56_5
-1
3
data56_4
-1
3
data56_3
-1
3
data56_2
-1
3
data56_1
-1
3
data56_0
-1
3
data55_7
-1
3
data55_6
-1
3
data55_5
-1
3
data55_4
-1
3
data55_3
-1
3
data55_2
-1
3
data55_1
-1
3
data55_0
-1
3
data54_7
-1
3
data54_6
-1
3
data54_5
-1
3
data54_4
-1
3
data54_3
-1
3
data54_2
-1
3
data54_1
-1
3
data54_0
-1
3
data53_7
-1
3
data53_6
-1
3
data53_5
-1
3
data53_4
-1
3
data53_3
-1
3
data53_2
-1
3
data53_1
-1
3
data53_0
-1
3
data52_7
-1
3
data52_6
-1
3
data52_5
-1
3
data52_4
-1
3
data52_3
-1
3
data52_2
-1
3
data52_1
-1
3
data52_0
-1
3
data51_7
-1
3
data51_6
-1
3
data51_5
-1
3
data51_4
-1
3
data51_3
-1
3
data51_2
-1
3
data51_1
-1
3
data51_0
-1
3
data50_7
-1
3
data50_6
-1
3
data50_5
-1
3
data50_4
-1
3
data50_3
-1
3
data50_2
-1
3
data50_1
-1
3
data50_0
-1
3
data4_7
-1
3
data4_6
-1
3
data4_5
-1
3
data4_4
-1
3