test.fit.qmsg

用fpga实现isp接口的源码

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.132 ns register register " "Info: Estimated most critical path is register to register delay of 9.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[1\] 1 REG LAB_X17_Y8 208 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y8; Fanout = 208; REG Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|xraddr\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[1] } "NODE_NAME" } } { "altdpram.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altdpram.tdf" 406 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.442 ns) 1.823 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|lpm_mux:mux\|mux_7hc:auto_generated\|w_result3127w~407 2 COMB LAB_X19_Y10 1 " "Info: 2: + IC(1.381 ns) + CELL(0.442 ns) = 1.823 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|lpm_mux:mux\|mux_7hc:auto_generated\|w_result3127w~407'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.823 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[1] SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result3127w~407 } "NODE_NAME" } } { "db/mux_7hc.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_7hc.tdf" 374 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.590 ns) 3.253 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|lpm_mux:mux\|mux_7hc:auto_generated\|w_result3127w~408 3 COMB LAB_X20_Y7 1 " "Info: 3: + IC(0.840 ns) + CELL(0.590 ns) = 3.253 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|lpm_mux:mux\|mux_7hc:auto_generated\|w_result3127w~408'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.430 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result3127w~407 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result3127w~408 } "NODE_NAME" } } { "db/mux_7hc.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_7hc.tdf" 374 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.064 ns) + CELL(0.590 ns) 3.907 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5688 4 COMB LAB_X20_Y7 1 " "Info: 4: + IC(0.064 ns) + CELL(0.590 ns) = 3.907 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5688'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.654 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result3127w~408 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5688 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.055 ns) + CELL(0.292 ns) 5.254 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5689 5 COMB LAB_X19_Y6 1 " "Info: 5: + IC(1.055 ns) + CELL(0.292 ns) = 5.254 ns; Loc. = LAB_X19_Y6; Fanout = 1; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5689'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.347 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5688 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5689 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.384 ns) + CELL(0.292 ns) 6.930 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5690 6 COMB LAB_X17_Y7 2 " "Info: 6: + IC(1.384 ns) + CELL(0.292 ns) = 6.930 ns; Loc. = LAB_X17_Y7; Fanout = 2; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5690'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.676 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5689 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5690 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.590 ns) 7.637 ns SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5691 7 COMB LAB_X17_Y7 2 " "Info: 7: + IC(0.117 ns) + CELL(0.590 ns) = 7.637 ns; Loc. = LAB_X17_Y7; Fanout = 2; COMB Node = 'SPI:inst\|RAM_TEST:inst2\|altdpram:altdpram_component\|alt_le_rden_reg:latch_emulator\|lpm_mux:latch_mux\|mux_lrd:auto_generated\|result_node\[5\]~5691'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.707 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5690 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5691 } "NODE_NAME" } } { "db/mux_lrd.tdf" "" { Text "F:/SPI/SPI_Byte_1/db/mux_lrd.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.738 ns) 9.132 ns SPI:inst\|spiprocess:inst21\|ramsendtemp\[5\] 8 REG LAB_X16_Y6 1 " "Info: 8: + IC(0.757 ns) + CELL(0.738 ns) = 9.132 ns; Loc. = LAB_X16_Y6; Fanout = 1; REG Node = 'SPI:inst\|spiprocess:inst21\|ramsendtemp\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5691 SPI:inst|spiprocess:inst21|ramsendtemp[5] } "NODE_NAME" } } { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 1493 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.534 ns ( 38.70 % ) " "Info: Total cell delay = 3.534 ns ( 38.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.598 ns ( 61.30 % ) " "Info: Total interconnect delay = 5.598 ns ( 61.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.132 ns" { SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[1] SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result3127w~407 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result3127w~408 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5688 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5689 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5690 SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[5]~5691 SPI:inst|spiprocess:inst21|ramsendtemp[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 15 " "Info: Average interconnect usage is 13% of the available device resources. Peak interconnect usage is 15%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "BUS_S:inst2\|lpm_bustri:lpm_bustri_component\|dout\[7\]~15 " "Info: Following pins have the same output enable: BUS_S:inst2\|lpm_bustri:lpm_bustri_component\|dout\[7\]~15" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[7\] LVTTL " "Info: Type bidirectional pin XDATA\[7\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[7\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[5\] LVTTL " "Info: Type bidirectional pin XDATA\[5\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[5\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[3\] LVTTL " "Info: Type bidirectional pin XDATA\[3\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[3\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[1\] LVTTL " "Info: Type bidirectional pin XDATA\[1\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[1\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[6\] LVTTL " "Info: Type bidirectional pin XDATA\[6\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[6\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[4\] LVTTL " "Info: Type bidirectional pin XDATA\[4\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[4\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[2\] LVTTL " "Info: Type bidirectional pin XDATA\[2\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[2\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional XDATA\[0\] LVTTL " "Info: Type bidirectional pin XDATA\[0\] uses the LVTTL I/O standard" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 232 920 1096 248 "XDATA\[7..0\]" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "XDATA\[0\]" } } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { XDATA[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 01 16:34:07 2006 " "Info: Processing ended: Fri Dec 01 16:34:07 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/SPI/SPI_Byte_1/TEST.fit.smsg " "Info: Generated suppressed messages file F:/SPI/SPI_Byte_1/TEST.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}