test.map.qmsg

用fpga实现isp接口的源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 01 16:33:27 2006 " "Info: Processing started: Fri Dec 01 16:33:27 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TEST -c TEST " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TEST -c TEST" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TEST.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file TEST.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TEST " "Info: Found entity 1: TEST" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "INTERFACE.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file INTERFACE.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 INTERFACE " "Info: Found entity 1: INTERFACE" {  } { { "INTERFACE.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/INTERFACE.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LEDRun.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LEDRun.v" { { "Info" "ISGN_ENTITY_NAME" "1 LEDRun " "Info: Found entity 1: LEDRun" {  } { { "LEDRun.v" "" { Text "F:/SPI/SPI_Byte_1/LEDRun.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DIFF_ONLY_IN_CASE" "ReceiveData Receivedata spiprocess.v(21) " "Info (10281): Verilog HDL Declaration information at spiprocess.v(21): object \"ReceiveData\" differs only in case from object \"Receivedata\" in the same scope" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "Receivedata spiprocess.v(44) " "Info (10151): Verilog HDL Declaration information at spiprocess.v(44): \"Receivedata\" is declared here" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 44 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spiprocess.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file spiprocess.v" { { "Info" "ISGN_ENTITY_NAME" "1 spiprocess " "Info: Found entity 1: spiprocess" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SPI.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SPI.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SPI " "Info: Found entity 1: SPI" {  } { { "SPI.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/SPI.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFOSEL.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIFOSEL.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFOSEL " "Info: Found entity 1: FIFOSEL" {  } { { "FIFOSEL.v" "" { Text "F:/SPI/SPI_Byte_1/FIFOSEL.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFOSEL_RD.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIFOSEL_RD.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFOSEL_RD " "Info: Found entity 1: FIFOSEL_RD" {  } { { "FIFOSEL_RD.v" "" { Text "F:/SPI/SPI_Byte_1/FIFOSEL_RD.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM_WR.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RAM_WR.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM_WR " "Info: Found entity 1: RAM_WR" {  } { { "RAM_WR.v" "" { Text "F:/SPI/SPI_Byte_1/RAM_WR.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM_RD.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RAM_RD.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM_RD " "Info: Found entity 1: RAM_RD" {  } { { "RAM_RD.v" "" { Text "F:/SPI/SPI_Byte_1/RAM_RD.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TEST " "Info: Elaborating entity \"TEST\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_PIN_IGNORED" "RESET1 " "Warning: Pin \"RESET1\" not connected" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 344 152 320 360 "RESET1" "" } { 336 320 381 352 "RESET1" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0}
{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst6 " "Warning: Primitive \"NOT\" of instance \"inst6\" not used" {  } { { "TEST.bdf" "" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 368 880 928 400 "inst6" "" } } } }  } 0 0 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SPI SPI:inst " "Info: Elaborating entity \"SPI\" for hierarchy \"SPI:inst\"" {  } { { "TEST.bdf" "inst" { Schematic "F:/SPI/SPI_Byte_1/TEST.bdf" { { 536 560 824 728 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spiprocess SPI:inst\|spiprocess:inst21 " "Info: Elaborating entity \"spiprocess\" for hierarchy \"SPI:inst\|spiprocess:inst21\"" {  } { { "SPI.bdf" "inst21" { Schematic "F:/SPI/SPI_Byte_1/SPI.bdf" { { 0 688 904 288 "inst21" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "RegNum spiprocess.v(63) " "Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(63): object \"RegNum\" assigned a value but never read" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 63 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "RegAddr1 spiprocess.v(65) " "Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(65): object \"RegAddr1\" assigned a value but never read" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 65 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "RegAddr2 spiprocess.v(66) " "Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(66): object \"RegAddr2\" assigned a value but never read" {  } { { "spiprocess.v" "" { Text "F:/SPI/SPI_Byte_1/spiprocess.v" 66 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}