test.tan.summary

用fpga实现isp接口的源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 14.651 ns
From           : ADDR[10]
To             : SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|cells[34][6]
From Clock     : --
To Clock       : WR
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.655 ns
From           : SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|cells[28][1]
To             : TEST8
From Clock     : WR
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 16.350 ns
From           : ADDR[10]
To             : XDATA[0]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.284 ns
From           : XDATA[4]
To             : SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|cells[11][4]
From Clock     : --
To Clock       : WR
Failed Paths   : 0

Type           : Clock Setup: 'GCLK'
Slack          : N/A
Required Time  : None
Actual Time    : 72.97 MHz ( period = 13.705 ns )
From           : SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0]
To             : SPI:inst|spiprocess:inst21|ramsendtemp[1]
From Clock     : GCLK
To Clock       : GCLK
Failed Paths   : 0

Type           : Clock Setup: 'RD'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : SPI:inst|spiprocess:inst21|outdata[0]
To             : SPI:inst|spiprocess:inst21|outdata[0]
From Clock     : RD
To Clock       : RD
Failed Paths   : 0

Type           : Clock Setup: 'RFirq'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : SPI:inst|spiprocess:inst21|T_ReceivesomeData2
To             : SPI:inst|spiprocess:inst21|T_ReceivesomeData2
From Clock     : RFirq
To Clock       : RFirq
Failed Paths   : 0

Type           : Clock Setup: 'WR'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : SPI:inst|spiprocess:inst21|CE
To             : SPI:inst|spiprocess:inst21|CE
From Clock     : WR
To Clock       : WR
Failed Paths   : 0

Type           : Clock Hold: 'GCLK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : SPI:inst|spiprocess:inst21|ReceiveData[3]
To             : SPI:inst|RAM7:inst10|altsyncram:altsyncram_component|altsyncram_jam1:auto_generated|ram_block1a7~porta_datain_reg4
From Clock     : GCLK
To Clock       : GCLK
Failed Paths   : 35

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 35

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