test.tan.rpt
来自「用fpga实现isp接口的源码」· RPT 代码 · 共 250 行 · 第 1/5 页
RPT
250 行
; N/A ; 94.21 MHz ( period = 10.615 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[4] ; SPI:inst|spiprocess:inst21|senddata[3] ; GCLK ; GCLK ; None ; None ; 5.938 ns ;
; N/A ; 94.22 MHz ( period = 10.613 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[5] ; SPI:inst|spiprocess:inst21|ramsendtemp[7] ; GCLK ; GCLK ; None ; None ; 5.936 ns ;
; N/A ; 94.27 MHz ( period = 10.608 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[3] ; SPI:inst|spiprocess:inst21|senddata[4] ; GCLK ; GCLK ; None ; None ; 5.931 ns ;
; N/A ; 94.46 MHz ( period = 10.586 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[4] ; SPI:inst|spiprocess:inst21|senddata[4] ; GCLK ; GCLK ; None ; None ; 5.909 ns ;
; N/A ; 94.69 MHz ( period = 10.561 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[5] ; SPI:inst|spiprocess:inst21|senddata[0] ; GCLK ; GCLK ; None ; None ; 5.884 ns ;
; N/A ; 95.54 MHz ( period = 10.467 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|a_hdffe:rden_reg|ldffe ; SPI:inst|spiprocess:inst21|senddata[6] ; GCLK ; GCLK ; None ; None ; 5.833 ns ;
; N/A ; 95.77 MHz ( period = 10.442 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[4] ; SPI:inst|spiprocess:inst21|senddata[6] ; GCLK ; GCLK ; None ; None ; 5.765 ns ;
; N/A ; 95.79 MHz ( period = 10.439 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[5] ; SPI:inst|spiprocess:inst21|senddata[5] ; GCLK ; GCLK ; None ; None ; 5.762 ns ;
; N/A ; 98.14 MHz ( period = 10.190 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|a_hdffe:rden_reg|ldffe ; SPI:inst|spiprocess:inst21|senddata[2] ; GCLK ; GCLK ; None ; None ; 5.556 ns ;
; N/A ; 98.18 MHz ( period = 10.185 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[0] ; SPI:inst|spiprocess:inst21|StatusReg0[2] ; GCLK ; GCLK ; None ; None ; 9.886 ns ;
; N/A ; 98.22 MHz ( period = 10.181 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[4] ; SPI:inst|spiprocess:inst21|senddata[7] ; GCLK ; GCLK ; None ; None ; 5.465 ns ;
; N/A ; 98.75 MHz ( period = 10.127 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|a_hdffe:rden_reg|ldffe ; SPI:inst|spiprocess:inst21|senddata[4] ; GCLK ; GCLK ; None ; None ; 5.493 ns ;
; N/A ; 99.22 MHz ( period = 10.079 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[2] ; SPI:inst|spiprocess:inst21|senddata[4] ; GCLK ; GCLK ; None ; None ; 5.402 ns ;
; N/A ; 99.51 MHz ( period = 10.049 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[4] ; SPI:inst|spiprocess:inst21|senddata[5] ; GCLK ; GCLK ; None ; None ; 5.372 ns ;
; N/A ; 99.68 MHz ( period = 10.032 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[2] ; SPI:inst|spiprocess:inst21|StatusReg0[2] ; GCLK ; GCLK ; None ; None ; 9.733 ns ;
; N/A ; 100.11 MHz ( period = 9.989 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[5] ; SPI:inst|spiprocess:inst21|senddata[6] ; GCLK ; GCLK ; None ; None ; 5.312 ns ;
; N/A ; 100.54 MHz ( period = 9.946 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[1] ; SPI:inst|spiprocess:inst21|StatusReg0[2] ; GCLK ; GCLK ; None ; None ; 9.647 ns ;
; N/A ; 100.60 MHz ( period = 9.940 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[0] ; SPI:inst|spiprocess:inst21|ReceiveAddr[0] ; GCLK ; GCLK ; None ; None ; 9.651 ns ;
; N/A ; 100.60 MHz ( period = 9.940 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[0] ; SPI:inst|spiprocess:inst21|ReceiveAddr[1] ; GCLK ; GCLK ; None ; None ; 9.651 ns ;
; N/A ; 100.60 MHz ( period = 9.940 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[0] ; SPI:inst|spiprocess:inst21|ReceiveAddr[2] ; GCLK ; GCLK ; None ; None ; 9.651 ns ;
; N/A ; 100.60 MHz ( period = 9.940 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[0] ; SPI:inst|spiprocess:inst21|ReceiveAddr[3] ; GCLK ; GCLK ; None ; None ; 9.651 ns ;
; N/A ; 100.60 MHz ( period = 9.940 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[0] ; SPI:inst|spiprocess:inst21|ReceiveAddr[4] ; GCLK ; GCLK ; None ; None ; 9.651 ns ;
; N/A ; 100.60 MHz ( period = 9.940 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[0] ; SPI:inst|spiprocess:inst21|ReceiveAddr[5] ; GCLK ; GCLK ; None ; None ; 9.651 ns ;
; N/A ; 100.81 MHz ( period = 9.920 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[5] ; SPI:inst|spiprocess:inst21|ramsendtemp[3] ; GCLK ; GCLK ; None ; None ; 5.243 ns ;
; N/A ; 101.51 MHz ( period = 9.851 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[3] ; SPI:inst|spiprocess:inst21|StatusReg0[2] ; GCLK ; GCLK ; None ; None ; 9.552 ns ;
; N/A ; 101.83 MHz ( period = 9.820 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[5] ; SPI:inst|spiprocess:inst21|senddata[3] ; GCLK ; GCLK ; None ; None ; 5.143 ns ;
; N/A ; 102.09 MHz ( period = 9.795 ns ) ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[5] ; SPI:inst|spiprocess:inst21|senddata[7] ; GCLK ; GCLK ; None ; None ; 5.079 ns ;
; N/A ; 102.18 MHz ( period = 9.787 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[2] ; SPI:inst|spiprocess:inst21|ReceiveAddr[0] ; GCLK ; GCLK ; None ; None ; 9.498 ns ;
; N/A ; 102.18 MHz ( period = 9.787 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[2] ; SPI:inst|spiprocess:inst21|ReceiveAddr[1] ; GCLK ; GCLK ; None ; None ; 9.498 ns ;
; N/A ; 102.18 MHz ( period = 9.787 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[2] ; SPI:inst|spiprocess:inst21|ReceiveAddr[2] ; GCLK ; GCLK ; None ; None ; 9.498 ns ;
; N/A ; 102.18 MHz ( period = 9.787 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[2] ; SPI:inst|spiprocess:inst21|ReceiveAddr[3] ; GCLK ; GCLK ; None ; None ; 9.498 ns ;
; N/A ; 102.18 MHz ( period = 9.787 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[2] ; SPI:inst|spiprocess:inst21|ReceiveAddr[4] ; GCLK ; GCLK ; None ; None ; 9.498 ns ;
; N/A ; 102.18 MHz ( period = 9.787 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[2] ; SPI:inst|spiprocess:inst21|ReceiveAddr[5] ; GCLK ; GCLK ; None ; None ; 9.498 ns ;
; N/A ; 103.08 MHz ( period = 9.701 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[1] ; SPI:inst|spiprocess:inst21|ReceiveAddr[0] ; GCLK ; GCLK ; None ; None ; 9.412 ns ;
; N/A ; 103.08 MHz ( period = 9.701 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[1] ; SPI:inst|spiprocess:inst21|ReceiveAddr[1] ; GCLK ; GCLK ; None ; None ; 9.412 ns ;
; N/A ; 103.08 MHz ( period = 9.701 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[1] ; SPI:inst|spiprocess:inst21|ReceiveAddr[2] ; GCLK ; GCLK ; None ; None ; 9.412 ns ;
; N/A ; 103.08 MHz ( period = 9.701 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[1] ; SPI:inst|spiprocess:inst21|ReceiveAddr[3] ; GCLK ; GCLK ; None ; None ; 9.412 ns ;
; N/A ; 103.08 MHz ( period = 9.701 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[1] ; SPI:inst|spiprocess:inst21|ReceiveAddr[4] ; GCLK ; GCLK ; None ; None ; 9.412 ns ;
; N/A ; 103.08 MHz ( period = 9.701 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[1] ; SPI:inst|spiprocess:inst21|ReceiveAddr[5] ; GCLK ; GCLK ; None ; None ; 9.412 ns ;
; N/A ; 103.46 MHz ( period = 9.666 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[5] ; SPI:inst|spiprocess:inst21|StatusReg0[2] ; GCLK ; GCLK ; None ; None ; 9.367 ns ;
; N/A ; 103.55 MHz ( period = 9.657 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[4] ; SPI:inst|spiprocess:inst21|StatusReg0[2] ; GCLK ; GCLK ; None ; None ; 9.358 ns ;
; N/A ; 104.10 MHz ( period = 9.606 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[3] ; SPI:inst|spiprocess:inst21|ReceiveAddr[0] ; GCLK ; GCLK ; None ; None ; 9.317 ns ;
; N/A ; 104.10 MHz ( period = 9.606 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[3] ; SPI:inst|spiprocess:inst21|ReceiveAddr[1] ; GCLK ; GCLK ; None ; None ; 9.317 ns ;
; N/A ; 104.10 MHz ( period = 9.606 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[3] ; SPI:inst|spiprocess:inst21|ReceiveAddr[2] ; GCLK ; GCLK ; None ; None ; 9.317 ns ;
; N/A ; 104.10 MHz ( period = 9.606 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[3] ; SPI:inst|spiprocess:inst21|ReceiveAddr[3] ; GCLK ; GCLK ; None ; None ; 9.317 ns ;
; N/A ; 104.10 MHz ( period = 9.606 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[3] ; SPI:inst|spiprocess:inst21|ReceiveAddr[4] ; GCLK ; GCLK ; None ; None ; 9.317 ns ;
; N/A ; 104.10 MHz ( period = 9.606 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[3] ; SPI:inst|spiprocess:inst21|ReceiveAddr[5] ; GCLK ; GCLK ; None ; None ; 9.317 ns ;
; N/A ; 106.25 MHz ( period = 9.412 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[4] ; SPI:inst|spiprocess:inst21|ReceiveAddr[0] ; GCLK ; GCLK ; None ; None ; 9.123 ns ;
; N/A ; 106.25 MHz ( period = 9.412 ns ) ; SPI:inst|spiprocess:inst21|sendFinishByte[4] ; SPI:inst|spiprocess:inst21|ReceiveAddr[1] ; GCLK ; GCLK ; None ; None ; 9.123 ns ;
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