test.tan.rpt

用fpga实现isp接口的源码

; Worst-case tco               ; N/A                                      ; None          ; 21.655 ns                                      ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|cells[28][1] ; TEST8                                                                                                              ; WR         ; --       ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 16.350 ns                                      ; ADDR[10]                                                         ; XDATA[0]                                                                                                           ; --         ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; -0.284 ns                                      ; XDATA[4]                                                         ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|cells[11][4]                                                   ; --         ; WR       ; 0            ;
; Clock Setup: 'GCLK'          ; N/A                                      ; None          ; 72.97 MHz ( period = 13.705 ns )               ; SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0]    ; SPI:inst|spiprocess:inst21|ramsendtemp[1]                                                                          ; GCLK       ; GCLK     ; 0            ;
; Clock Setup: 'RD'            ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SPI:inst|spiprocess:inst21|outdata[0]                            ; SPI:inst|spiprocess:inst21|outdata[0]                                                                              ; RD         ; RD       ; 0            ;
; Clock Setup: 'RFirq'         ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SPI:inst|spiprocess:inst21|T_ReceivesomeData2                    ; SPI:inst|spiprocess:inst21|T_ReceivesomeData2                                                                      ; RFirq      ; RFirq    ; 0            ;
; Clock Setup: 'WR'            ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SPI:inst|spiprocess:inst21|CE                                    ; SPI:inst|spiprocess:inst21|CE                                                                                      ; WR         ; WR       ; 0            ;
; Clock Hold: 'GCLK'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; SPI:inst|spiprocess:inst21|ReceiveData[3]                        ; SPI:inst|RAM7:inst10|altsyncram:altsyncram_component|altsyncram_jam1:auto_generated|ram_block1a7~porta_datain_reg4 ; GCLK       ; GCLK     ; 35           ;
; Total number of failed paths ;                                          ;               ;                                                ;                                                                  ;                                                                                                                    ;            ;          ; 35           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; GCLK            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; WR              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; RFirq           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; RD              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+