📄 spiprocess.v
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mosi=senddata[0];
bitcounter=bitcounter+5'b1;
end
6'b01111:
begin
SCK=1'b1;
StatusReg0[0]=miso;
bitcounter=bitcounter+5'b1;
senddata=ramsendtemp;
end
6'b10000:
begin
SCK=1'b0;
bitcounter=5'b0;
ramdReceivetemp=StatusReg0;
sendFinishByte=sendFinishByte+6'b1;
receiveByte=receiveByte+6'b1;
end
endcase
end
end
else if(sendFinishByte<(SendByteNum-1)) //发送中间字节
begin
case(bitcounter)
5'b00000:
begin
SCK=1'b0;
mosi=senddata[7];
SendramCLK=1'b0;
SendRDen=1'b1;
bitcounter=bitcounter+5'b1;
end
5'b00001:
begin
SCK=1'b0;
bitcounter=bitcounter+5'b1;
SendramCLK=1'b1;
end
5'b00010:
begin
SCK=1'b1;
StatusReg0[7]=miso;
bitcounter=bitcounter+5'b1;
end
5'b00011:
begin
SCK=1'b0;
mosi=senddata[6];
bitcounter=bitcounter+5'b1;
ramsendtemp=ramindata; //读取下一个数据
end
5'b00100:
begin
SCK=1'b1;
StatusReg0[6]=miso;
bitcounter=bitcounter+5'b1;
SendAddr=SendAddr+6'b1;
SendramCLK=1'b0;
SendRDen=1'b0;
end
5'b00101:
begin
SCK=1'b0;
mosi=senddata[5];
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b0;
ReceiveWen=1'b1; //准备写入收到的数据
end
5'b00110:
begin
SCK=1'b1;
StatusReg0[5]=miso;
bitcounter=bitcounter+5'b1;
end
5'b00111:
begin
SCK=1'b0;
mosi=senddata[4];
bitcounter=bitcounter+5'b1;
ReceiveData=ramdReceivetemp; //准备好写入的数据（在时钟上升沿到来前，将数据放到总线上）
end
5'b01000:
begin
SCK=1'b1;
StatusReg0[4]=miso;
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b1; //第一次写入（为了安全，每个数据写两次）
end
5'b01001:
begin
SCK=1'b0;
mosi=senddata[3];
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b0;
end
5'b01010:
begin
SCK=1'b1;
StatusReg0[3]=miso;
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b1; //第二次写入（为了安全，每个数据写两次）
end
5'b01011:
begin
SCK=1'b0;
mosi=senddata[2];
bitcounter=bitcounter+5'b1;
ReceiveAddr=ReceiveAddr+6'b1;
ReceiveCLK=1'b0;
ReceiveWen=1'b0; //取消写ram信号
end
5'b01100:
begin
SCK=1'b1;
StatusReg0[2]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01101:
begin
SCK=1'b0;
mosi=senddata[1];
bitcounter=bitcounter+5'b1;
end
5'b01110:
begin
SCK=1'b1;
StatusReg0[1]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01111:
begin
SCK=1'b0;
mosi=senddata[0];
bitcounter=bitcounter+5'b1;
end
6'b10000:
begin
SCK=1'b1;
StatusReg0[0]=miso;
bitcounter=bitcounter+5'b1;
end
6'b10001:
begin
SCK=1'b0;
bitcounter=5'b0;
sendFinishByte=sendFinishByte+6'b1;
ramdReceivetemp=StatusReg0;
senddata=ramsendtemp;
receiveByte=receiveByte+6'b1;
end
endcase
end
else if(sendFinishByte==(SendByteNum-1)) //发送最后一个字节
begin
case(bitcounter)
5'b00000:
begin
SCK=1'b0;
mosi=senddata[7];
bitcounter=bitcounter+5'b1;
end
5'b00001:
begin
bitcounter=bitcounter+5'b1;
end
5'b00010:
begin
SCK=1'b1;
StatusReg0[7]=miso;
bitcounter=bitcounter+5'b1;
end
5'b00011:
begin
SCK=1'b0;
mosi=senddata[6];
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b0;
ReceiveWen=1'b1; //准备写入收到的数据
ReceiveData=ramdReceivetemp;
end
5'b00100:
begin
SCK=1'b1;
StatusReg0[6]=miso;
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b1; //第一次写入（为了安全，每个数据写两次）
end
5'b00101:
begin
SCK=1'b0;
mosi=senddata[5];
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b0;
end
5'b00110:
begin
SCK=1'b1;
StatusReg0[5]=miso;
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b1; //第二次写入（为了安全，每个数据写两次）
end
5'b00111:
begin
SCK=1'b0;
mosi=senddata[4];
bitcounter=bitcounter+5'b1;
ReceiveAddr=ReceiveAddr+6'b1;
ReceiveCLK=1'b0;
ReceiveWen=1'b0; //取消写ram信号
end
5'b01000:
begin
SCK=1'b1;
StatusReg0[4]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01001:
begin
SCK=1'b0;
mosi=senddata[3];
bitcounter=bitcounter+5'b1;
end
5'b01010:
begin
SCK=1'b1;
StatusReg0[3]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01011:
begin
SCK=1'b0;
mosi=senddata[2];
bitcounter=bitcounter+5'b1;
end
5'b01100:
begin
SCK=1'b1;
StatusReg0[2]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01101:
begin
SCK=1'b0;
mosi=senddata[1];
bitcounter=bitcounter+5'b1;
end
5'b01110:
begin
SCK=1'b1;
StatusReg0[1]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01111:
begin
SCK=1'b0;
mosi=senddata[0];
bitcounter=bitcounter+5'b1;
end
6'b10000:
begin
SCK=1'b1;
StatusReg0[0]=miso;
ramdReceivetemp=StatusReg0;
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b0;
ReceiveWen=1'b1; //准备写入收到的数据
ReceiveData=ramdReceivetemp;
end
6'b10001:
begin
SCK=1'b0;
bitcounter=bitcounter+5'b1;
//写入的数据已经发送完毕，将接收到的最后一个数据写RAM中
ReceiveCLK=1'b1; //第一次写入（为了安全，每个数据写两次）
end
6'b10010:
begin
CSN=1'b1;
bitcounter=bitcounter+5'b1;
ReceiveCLK=1'b0;
end
6'b10011:
begin
ReceiveCLK=1'b1; //第二次写入（为了安全，每个数据写两次）
bitcounter=bitcounter+5'b1;
end
6'b10100:
begin
ready=1'b0;
bitcounter=5'b0;
senddatastart=senden;
sendfilish=1;
receiveByte=receiveByte+6'b1;
ReceiveAddr=6'b0;
ReceiveCLK=1'b0;
ReceiveWen=1'b0; //取消写ram信号
ReceiveReady=1'b1;
end
endcase
end
end
end
else if(sendfilish==1) //如果没有数据要发送，那么就循环的读取寄存器中的值，此时最好配置射频在接收的状态。
begin
end
end
end
endmodule
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