📄 test.map.rpt
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; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Integer ;
; WIDTHAD_B ; 6 ; Integer ;
; NUMWORDS_B ; 64 ; Integer ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_jam1 ; Untyped ;
+------------------------------------+-----------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: INTERFACE:inst1|tritest8:inst|lpm_bustri:lpm_bustri_component ;
+----------------+-------+-----------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------------------------------------------+
; LPM_WIDTH ; 8 ; Integer ;
+----------------+-------+-----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: BUS_S:inst2|lpm_bustri:lpm_bustri_component ;
+----------------+-------+-----------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------------------------+
; LPM_WIDTH ; 8 ; Integer ;
+----------------+-------+-----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: counter25:inst5|lpm_counter:lpm_counter_component ;
+------------------------+-------------+---------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+---------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 25 ; Integer ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; cntr_dth ; Untyped ;
+------------------------+-------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
Info: Processing started: Fri Dec 01 16:33:27 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TEST -c TEST
Info: Found 1 design units, including 1 entities, in source file TEST.bdf
Info: Found entity 1: TEST
Info: Found 1 design units, including 1 entities, in source file INTERFACE.bdf
Info: Found entity 1: INTERFACE
Info: Found 1 design units, including 1 entities, in source file LEDRun.v
Info: Found entity 1: LEDRun
Info (10151): Verilog HDL Declaration information at spiprocess.v(44): "Receivedata" is declared here
Info: Found 1 design units, including 1 entities, in source file spiprocess.v
Info: Found entity 1: spiprocess
Info: Found 1 design units, including 1 entities, in source file SPI.bdf
Info: Found entity 1: SPI
Info: Found 1 design units, including 1 entities, in source file FIFOSEL.v
Info: Found entity 1: FIFOSEL
Info: Found 1 design units, including 1 entities, in source file FIFOSEL_RD.v
Info: Found entity 1: FIFOSEL_RD
Info: Found 1 design units, including 1 entities, in source file RAM_WR.v
Info: Found entity 1: RAM_WR
Info: Found 1 design units, including 1 entities, in source file RAM_RD.v
Info: Found entity 1: RAM_RD
Info: Elaborating entity "TEST" for the top level hierarchy
Warning: Pin "RESET1" not connected
Warning: Primitive "NOT" of instance "inst6" not used
Info: Elaborating entity "SPI" for hierarchy "SPI:inst"
Info: Elaborating entity "spiprocess" for hierarchy "SPI:inst|spiprocess:inst21"
Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(63): object "RegNum" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(65): object "RegAddr1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(66): object "RegAddr2" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(67): object "RegAddr3" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(68): object "RegAddr4" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(70): object "ReceiveReady" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at spiprocess.v(79): object "T_ReceivesomeData3" assigned a value but never read
Warning: Using design file RAM_TEST.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: RAM_TEST
Info: Elaborating entity "RAM_TEST" for hierarchy "SPI:inst|RAM_TEST:inst2"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus60/libraries/megafunctions/altdpram.tdf
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