test.fit.summary

用fpga实现isp接口的源码

Fitter Status : Successful - Fri Dec 01 16:34:07 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Web Edition
Revision Name : TEST
Top-level Entity Name : TEST
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 1,075 / 2,910 ( 37 % )
Total pins : 49 / 104 ( 47 % )
Total virtual pins : 0
Total memory bits : 512 / 59,904 ( < 1 % )
Total PLLs : 0 / 1 ( 0 % )