test.sim.rpt

用fpga实现isp接口的源码

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; |TEST|SPI:inst|spiprocess:inst21|mosi                                                                                                                 ; |TEST|SPI:inst|spiprocess:inst21|mosi                                                                                                                 ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|SCK                                                                                                                  ; |TEST|SPI:inst|spiprocess:inst21|SCK                                                                                                                  ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|sendfinishtest                                                                                                       ; |TEST|SPI:inst|spiprocess:inst21|sendfinishtest                                                                                                       ; regout           ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1021w~47                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1021w~47                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1021w~48                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1021w~48                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1019w~44                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1019w~44                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1019w~45                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1019w~45                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5619 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5619 ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1103w~281                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1103w~281                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1103w~282                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1103w~282                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5622 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5622 ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5623 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5623 ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result825w~49                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result825w~49                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result825w~50                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result825w~50                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result823w~44                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result823w~44                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result823w~45                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result823w~45                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5625 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5625 ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result907w~407                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result907w~407                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result907w~408                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result907w~408                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5628 ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5629 ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~645                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~645                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~645                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[2]                                                                                   ; regout           ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result923w~47                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result923w~47                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result923w~47                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[0]                                                                                   ; regout           ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result923w~48                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result923w~48                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result722w~47                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result722w~47                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result722w~48                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result722w~48                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~646                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~646                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result921w~44                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result921w~44                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result921w~44                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[1]                                                                                   ; regout           ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result921w~45                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result921w~45                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result720w~44                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result720w~44                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result720w~45                                          ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result720w~45                                          ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~647                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~647                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~648                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~648                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~649                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~649                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~649                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|xraddr[3]                                                                                   ; regout           ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1005w~281                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1005w~281                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1005w~282                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1005w~282                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result805w~281                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result805w~281                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result805w~282                                         ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result805w~282                                         ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~650                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~650                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~651                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~651                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~652                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~652                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~656                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~656                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~657                                        ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|lpm_mux:mux|mux_7hc:auto_generated|w_result1115w~657                                        ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5630 ; combout          ;
; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 ; |TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component|alt_le_rden_reg:latch_emulator|lpm_mux:latch_mux|mux_lrd:auto_generated|result_node[1]~5631 ; combout          ;
; |TEST|SPI:inst|spiprocess:inst21|senddata[4]                                                                                                          ; |TEST|SPI:inst|spiprocess:inst21|senddata[4]                                                                                                          ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|bitcounter[2]                                                                                                        ; |TEST|SPI:inst|spiprocess:inst21|bitcounter[2]                                                                                                        ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|senddata[2]                                                                                                          ; |TEST|SPI:inst|spiprocess:inst21|senddata[2]                                                                                                          ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|senddata[6]                                                                                                          ; |TEST|SPI:inst|spiprocess:inst21|senddata[6]                                                                                                          ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|Selector38~584                                                                                                       ; |TEST|SPI:inst|spiprocess:inst21|Selector38~584                                                                                                       ; combout          ;
; |TEST|SPI:inst|spiprocess:inst21|senddata[0]                                                                                                          ; |TEST|SPI:inst|spiprocess:inst21|senddata[0]                                                                                                          ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|Selector38~585                                                                                                       ; |TEST|SPI:inst|spiprocess:inst21|Selector38~585                                                                                                       ; combout          ;
; |TEST|SPI:inst|spiprocess:inst21|senddata[1]                                                                                                          ; |TEST|SPI:inst|spiprocess:inst21|senddata[1]                                                                                                          ; regout           ;
; |TEST|SPI:inst|spiprocess:inst21|senddata[5]                                                                                                          ; |TEST|SPI:inst|spiprocess:inst21|senddata[5]                                                                                                          ; regout           ;