left_right_leds.par

xilinx的SPARTAN-3E入门开发板实例 根据官方公布的led移动范例改写。 原范例仅提供了源代码、烧写文件以及dos窗口下使用的烧写bat文件。 本实例采用了ise7.1i创建

Release 7.1.04i par H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

HAN::  Tue Dec 26 22:56:03 2006

par -w -intstyle ise -ol std -t 1 left_right_leds_map.ncd left_right_leds.ncd
left_right_leds.pcf 


Constraints file: left_right_leds.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment
C:/Xilinx.
   "left_right_leds" is an NCD, version 3.1, device xc3s500e, package fg320,
speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.13 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 24      4%
   Number of External IBUFs            4 out of 232     1%
      Number of LOCed IBUFs            4 out of 4     100%

   Number of External IOBs             8 out of 176     4%
      Number of LOCed IOBs             8 out of 8     100%

   Number of Slices                   14 out of 4656    1%
      Number of SLICEMs                0 out of 2328    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 6 secs 
Finished initial Timing Analysis.  REAL time: 6 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896eb) REAL time: 6 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.2
......
.................


Phase 3.2 (Checksum:98a243) REAL time: 10 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 10 secs 

Phase 5.8
.
.
Phase 5.8 (Checksum:990204) REAL time: 10 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 10 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs 

Writing design to file left_right_leds.ncd


Total REAL time to Placer completion: 10 secs 
Total CPU time to Placer completion: 10 secs 

Starting Router

Phase 1: 95 unrouted;       REAL time: 13 secs 

Phase 2: 70 unrouted;       REAL time: 13 secs 

Phase 3: 10 unrouted;       REAL time: 13 secs 

Phase 4: 10 unrouted; (0)      REAL time: 13 secs 

Phase 5: 10 unrouted; (0)      REAL time: 13 secs 

Phase 6: 10 unrouted; (0)      REAL time: 13 secs 

Phase 7: 0 unrouted; (0)      REAL time: 13 secs 

Phase 8: 0 unrouted; (0)      REAL time: 13 secs 


Total REAL time to Router completion: 13 secs 
Total CPU time to Router completion: 13 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP | BUFGMUX_X1Y11| No   |   24 |  0.020     |  1.070      |
+---------------------+--------------+------+------+------------+-------------+


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.394
   The MAXIMUM PIN DELAY IS:                               5.829
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.366

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
          31          51           3           0           8           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "clk_BUFGP/IBUFG" PERIOD = 20 ns HIGH | 20.000ns   | 7.240ns    | 1    
   50%                                      |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 14 secs 
Total CPU time to PAR completion: 13 secs 

Peak Memory Usage:  122 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file left_right_leds.ncd



PAR done!