lfsr_a.vhd

来自「The objective of this projectis to desig」· VHDL 代码 · 共 28 行

 library ieee;
 use ieee.std_logic_1164.all;
 entity lfsr is

port(
	clk,load,shift : in std_logic;
	din: in std_logic_vector(0 to 3);
        dout: out std_logic_vector(0 to 3));
       
END LFSR ;
ARCHITECTURE bsr of LFSR is
  signal tmp4 :std_logic_vector(3 downto 0);
 
  
begin
  posedge: PROCESS (clk, load,shift)
  begin
  
    if (load'event and load='1') and (clk'event and clk='1') then
      tmp4(3)<=  DIN(0) xor din(1) ;
      tmp4(0) <= din(1);
      tmp4(1) <= din(2);
      tmp4(2) <=din(3);
      dout <=tmp4;
      end if;
END process;
    end bsr;