auto.vhd

来自「The objective of this projectis to desig」· VHDL 代码 · 共 57 行

use work.all;

entity AUTO is
  port( B: in BIT_VECTOR(3 downto 0);
        CLK: in BIT;
        Acout: out BIT_VECTOR(2 downto 0));
      
 end auto;
 

architecture behave of AUTO is

function LFSR_A(LFSR_IN :Bit_vector(3 downto 0)) return Bit_vector 
  is
    variable temp:BIT_VECTOR(3 DOWNTO 0);
    variable FEEDBACK :BIT;
    begin
    
    		temp(3 downto 0) :=LFSR_in(3 downto 0);
    		feedback :=LFSR_in(0) xor LFSR_in(1);
    		temp(0) :=LFSR_in(1) ;
    		temp(1) :=LFSR_in(2);
    		temp(2) :=LFSR_in(3);
    		temp(3) :=feedback;
    		RETURN TEMP;
    	end LFSR_A;
   
   begin
   process(clk)
   variable temp: BIT_VECTOR(3 downto 0);
   variable CNT: integer :=0;
   
      begin 
        if CLK'event and CLK='1' then
          temp :=LFSR_A(temp);
          for I in 0 to 3 loop
            if temp(i)= B(i) then
            CNT :=CNT+1;
            end if;
          end loop;
          
          case CNT is
              when 0 => ACOUT <= "000";
              when 1 => ACOUT <= "001";
              when 2 => ACOUT <= "010";
              when 3 => ACOUT <= "011";
              when 4 => ACOUT <= "100";
              WHEN OTHERS => ACOUT <="111";
           end case;
           end if;
      end process;
    end BEHAVE;