📄 testbench_struc.vhd
字号:
entity TEST_BENCH isend TEST_BENCH;use work.all;architecture AUTOCOR1 of TEST_BENCH is signal B,M1,M2,M3: BIT_VECTOR(3 downto 0); signal A: BIT_VECTOR(2 downto 0); SIGNAL RUN:BIT; SIGNAL RESET:BIT; SIGNAL LOAD:BIT; SIGNAL CLK:BIT; SIGNAL SHIFT: BIT; component OSCILLATOR generic (HI_TIME,LO_TIME:TIME); port (RUN: in BIT; CLOCK: out BIT :='0'); end component; component shifterc port(B: in BIT_VECTOR(3 downto 0); LOAD,SHIFT,CLK,RESET: in BIT; SR:out BIT_VECTOR(3 downto 0)); end component; component REG_nc port(B:in BIT_VECTOR(3 downto 0); LOAD,CLK,RESET: in BIT; REG_OUT: out BIT_VECTOR(3 downto 0)); end component; component compc port(sr: in BIT_VECTOR(3 downto 0); REG_OUT: in BIT_VECTOR(3 downto 0); XNOR_OUT:out BIT_VECTOR(3 downto 0)); end component; component cntc port(XNOR_OUT: in BIT_VECTOR(3 downto 0); A: out BIT_VECTOR(2 downto 0)); end component; for L1: OSCILLATOR use entity COSC(ALG); for L2: shifterc use entity shifter_a(BEH); for L3: REG_nc use entity REG_n(beh); for L4: COMPc use entity COMP(BEH); for L5: cntc use entity cnt(beh); begin L1: OSCILLATOR generic map(100 ns, 100 ns) port map(RUN,CLK); L2: shifterc port map(B,LOAD,SHIFT,CLK,RESET,M2); L3:REG_nc port map(B,LOAD,CLK,RESET,M1); L4:compc port map(M1,M2,M3); L5:cntc port map(M3,A); RESET <= '0','1' after 1000 ns,'0' after 1200 ns; RUN <= '1','0' after 4000 ns; B <= "0110";--, -- "0101" after 3400 ns; -- "0110" after 1600 ns, -- "0111" after 2400 ns; -- "0110" after 2400 ns; LOAD <= '1','0'after 200 ns;--,'1' after 3400 ns,'0'after 3600 ns;--, '1' after 1600 ns,'0' after 1650 ns,'1' after 2400 ns,'0' after 2450 ns; SHIFT <= '0','1' after 200 ns;--,'0' after 3400 ns,'1' after 3600 ns ; end AUTOCOR1;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -