dff.vhd

来自「The objective of this projectis to desig」· VHDL 代码 · 共 30 行

-- DFF model


USE WORK.ALL;
entity DFF is
   generic(constant TPHLRE:TIME:=10 ns;
           constant TPLH:TIME:=12 ns;
	   constant TPHL:TIME:=14 ns);
   port (D, clk ,reset : in BIT;
  	 Q :out BIT);
end DFF;

architecture BEH of DFF is 
begin
P1: process(clk)
variable Q_TEM:BIT:='0';
	begin
	if (clk'event and clk='1') then
	  if (Q_TEM='0' and D='1') then 
	    Q <=D after TPLH;
	     elsif (Q_TEM='1' and D='0') then
	      Q <= D after TPHL;
	       else 
	        Q <=D;
           end if;
           Q_TEM := D;
	end if;
    end process P1;
end BEH;