cosc.vhd

来自「The objective of this projectis to desig」· VHDL 代码 · 共 18 行

entity COSC is
 generic( Hi_time , lo_time:time);
 port(Run: in BIT; CLocK: out BIT :='0');
end COSC;
architecture ALG of COSC is
begin
 process
 begin
  wait until RUN='1';
  while RUN='1' loop
    CLocK <= '1';
    wait for HI_TIME;
    CLocK <='0';
    wait for LO_TIME;
  	 end loop;
     end process;
   end ALG;