reg_n.vhd

The objective of this projectis to design, model and simulate an autocorrelation generator circuit

USE WORK.ALL;
entity DFF is
   generic(constant TPHLRE:TIME:=10 ns;
           constant TPLH:TIME:=12 ns;
	   constant TPHL:TIME:=14 ns);
   port (D, clk ,reset : in BIT;
  	 Q :out BIT);
end DFF;

architecture BEH of DFF is 
begin
P1: process(clk)
variable Q_TEM:BIT;
	begin
	if (clk'event and clk='1') then
	  
	    Q <=D ;
	     
	end if;
    end process P1;
end BEH;


---REG
USE WORK.ALL;
entity REG_n is
port (B: in BIT_VECTOR(3 DOWNTO 0);
      load: in BIT;
      clk:in BIT;
      reset:in BIT;
       reg_out: out BIT_VECTOR(3 downto 0));
end REG_n;

architecture BEH of REG_n is
   component and2c
   port(I1,I2:in BIT; O: out BIT);
   end component;
   
   component dffc
   port (D, clk ,reset : in BIT;
  	 Q : out BIT);
   end component;
   
   
   for all : dffc use entity work.DFF(BEH);
   for all : AND2C use entity AND2(BEH);
   signal A0,A1,A2,A3,A4,A5,A6,A7: BIT;
   
   
begin
--FIRST INPUT
G0: AND2C
        port map (load, B(0), A0);

G1: AND2C
        port map (load, B(1), A1);
        
G2: AND2C
        port map (load, B(2), A2);        
        
G3: AND2C
        port map (load, B(3), A3);       
        
-- SECOND INPUT       

G4: DFFC
	port map (A0, clk ,reset, A4);   
        
G5: DFFC
	port map (A1, clk ,reset, A5);          
                
G6: DFFC
	port map (A2, clk ,reset, A6);        
                
G15: DFFC
	port map (A3, clk ,reset, A7);  

reg_out(0)<=A4;
reg_out(1)<=A5;
reg_out(2)<=A6;
reg_out(3)<=A7;

END BEH;