reg.vhd

The objective of this projectis to design, model and simulate an autocorrelation generator circuit

-- DFF model

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity DFF is
   generic(constant TPHLRE:TIME:=10 ns;
           constant TPLH:TIME:=12 ns;
	   constant TPHL:TIME:=14 ns);
   port (D, clk ,reset : in std_logic;
  	 Q : out std_logic);
end DFF;

architecture BEH of DFF is 
begin
P1: process(clk)
variable Q_TEM:STD_LOGIC:='0';
	begin
	if (clk'event and clk='1') then
	  if (Q_TEM='0' and D='1') then 
	    Q <=D after TPLH;
	     elsif (Q_TEM='1' and D='0') then
	      Q <= D after TPHL;
	       else 
	        Q <=D;
           end if;
           Q_TEM := D;
	end if;
    end process P1;
end BEH;

 
---REG
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity REG is
port (X: in std_logic_VECTOR(3 DOWNTO 0);
      clk: in std_logic;
      reset: in std_logic;
       Z: out STD_LOGIC_VECTOR);
end REG;

architecture BEH of REG is
   component dffc
   port (D, clk ,reset : in std_logic;
  	 Q : out std_logic);
   end component;
   for all : dffc use entity work.DFF(BEH);
   signal REG_OUT: STD_LOGIC_VECTOR(3 DOWNTO 0);
   
begin

REG_DFF0: DFFC
        port map (X(0), CLK, reset, REG_OUT(0));
REG_DFF1: DFFC
        port map (X(1), CLK, reset,REG_OUT(1));
REG_DFF2: DFFC
        port map (X(2), CLK, reset,REG_OUT(2));
REG_DFF3: DFFC
        port map (X(3), CLK, reset,REG_OUT(3));

Z <= REG_OUT;

END BEH;