and2.vhd

来自「The objective of this projectis to desig」· VHDL 代码 · 共 28 行

--AND2 MODEL
USE WORK.ALL;
entity AND2 is
    generic(constant TPLH:TIME:=4 ns;
            constant TPHL:TIME:=6 ns);	
    port ( I1,I2:in BIT; O: out BIT);
end AND2;

architecture BEH of AND2 IS
begin
P1: process(I1)
variable O_TEM:BIT:='0';
variable O_TEM_M:BIT;
 
	BEGIN
	O_TEM_M := I1 AND I2 ;
	if ( O_TEM='0' AND O_TEM_M='1') then
	   O <= I1 AND I2 after TPLH;
	   elsif (O_TEM='1' AND O_TEM_M='0') then
	        O <= I1 AND I2 after TPHL; 
	        else O <= I1 AND I2 ;
	 end if;
	  O_TEM:= I1 AND I2 ;
end process P1;
end BEH;