led_decode.v

用veilog HDL编的七段译码显示电路。自己做的第一个此类程序

module led_decode(clk,reset,a,b,c,d,e,f,g);

output a,b,c,d,e,f,g;
input clk,reset;
reg [3:0] D;
reg a,b,c,d,e,f,g;
always@(posedge clk)
begin
if (!reset) D[3:0]<=0;
else if (D[3:0]==9)
D[3:0]<=0;
else D[3:0]<=D[3:0]+1;
end

 always @ (D[3:0])
  begin
  case(D[3:0])
    4'd0:{a,b,c,d,e,f,g}=7'b1111110;
    4'd1:{a,b,c,d,e,f,g}=7'b0110000;
    4'd2:{a,b,c,d,e,f,g}=7'b1101101;
    4'd3:{a,b,c,d,e,f,g}=7'b1111001;
    4'd4:{a,b,c,d,e,f,g}=7'b0110011;
    4'd5:{a,b,c,d,e,f,g}=7'b1011011;
    4'd6:{a,b,c,d,e,f,g}=7'b1011111;
    4'd7:{a,b,c,d,e,f,g}=7'b1110000;
    4'd8:{a,b,c,d,e,f,g}=7'b1111111;
    4'd9:{a,b,c,d,e,f,g}=7'b1111011;
    default:{a,b,c,d,e,f,g}=7'bx;
  endcase
end
  endmodule