dcfq.fit.rpt

经典触发器

+------+----------+---------------+---------------+-----------------------+-----+


+---------------------------------------------------+
; Pad To Core Delay Chain Fanout                    ;
+----------------------------------------------------
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; D                   ;                   ;         ;
;      - Q~reg0       ; 1                 ; ON      ;
; CLK                 ;                   ;         ;
;      - Q~reg0       ; 0                 ; OFF     ;
+---------------------+-------------------+---------+


+--------------------------------------------------------------------------------------+
; Control Signals                                                                      ;
+---------------------------------------------------------------------------------------
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------+----------+---------+-------+--------+----------------------+------------------+
; CLK  ; Pin_24   ; 1       ; Clock ; no     ; --                   ; --               ;
+------+----------+---------+-------+--------+----------------------+------------------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------------------
; Name   ; Fan-Out                ;
+--------+------------------------+
; CLK    ; 1                      ;
; D      ; 1                      ;
; Q~reg0 ; 1                      ;
+--------+------------------------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------------------------------
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; C4s                        ; 1 / 8,840 ( < 1 % )  ;
; Direct links               ; 0 / 11,506 ( 0 % )   ;
; Global clocks              ; 0 / 8 ( 0 % )        ;
; LAB clocks                 ; 0 / 156 ( 0 % )      ;
; LUT chains                 ; 0 / 2,619 ( 0 % )    ;
; Local interconnects        ; 3 / 11,506 ( < 1 % ) ;
; M4K buffers                ; 0 / 468 ( 0 % )      ;
; R4s                        ; 0 / 7,520 ( 0 % )    ;
+----------------------------+----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 1                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 2.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+------------------+
; Fitter Messages  ;
+------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Dec 21 16:50:14 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off DCFQ -c DCFQ
Info: Selected device EP1C3T100C6 for design DCFQ
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
Info: No exact pin location assignment(s) for 3 pins of 3 total pins
    Info: Pin Q not assigned to an exact location on the device
    Info: Pin D not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency
Info: Performing register packing on non-logic cell registers with location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP Scan-chain Inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF
    Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 2 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  16 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Details of I/O bank after I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  8 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  16 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Dec 21 16:50:27 2006
    Info: Elapsed time: 00:00:12