dcfq.vhd

来自「经典触发器」· VHDL 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCFQ IS
   PORT(CLK:IN STD_LOGIC;
         D:IN STD_LOGIC;
         Q:OUT STD_LOGIC);
END DCFQ;
ARCHITECTURE ART1 OF DCFQ IS
   BEGIN
   PROCESS(CLK)
   BEGIN
     IF(CLK'EVENT AND CLK='1')THEN
        Q<=D;
      END IF;
    END PROCESS;
END ART1;