dcfq.map.qmsg

经典触发器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 21 16:50:05 2006 " "Info: Processing started: Thu Dec 21 16:50:05 2006" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off DCFQ -c DCFQ " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DCFQ -c DCFQ" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DCFQ.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file DCFQ.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DCFQ-ART1 " "Info: Found design unit 1: DCFQ-ART1" {  } { { "d:/quartus/dcfq项目/DCFQ.vhd" "DCFQ-ART1" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DCFQ " "Info: Found entity 1: DCFQ" {  } { { "d:/quartus/dcfq项目/DCFQ.vhd" "DCFQ" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "4 " "Info: Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 21 16:50:11 2006 " "Info: Processing ended: Thu Dec 21 16:50:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}