dcfq.tan.qmsg

经典触发器

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q Q~reg0 5.323 ns register " "Info: tco from clock CLK to destination pin Q through register Q~reg0 is 5.323 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.303 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 2.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.547 ns) 2.303 ns Q~reg0 2 REG LC_X1_Y1_N2 1 " "Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "1.173 ns" { CLK Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 72.82 % " "Info: Total cell delay = 1.677 ns ( 72.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.626 ns 27.18 % " "Info: Total interconnect delay = 0.626 ns ( 27.18 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.847 ns + Longest register pin " "Info: + Longest register to pin delay is 2.847 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q~reg0 1 REG LC_X1_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(1.634 ns) 2.847 ns Q 2 PIN Pin_22 0 " "Info: 2: + IC(1.213 ns) + CELL(1.634 ns) = 2.847 ns; Loc. = Pin_22; Fanout = 0; PIN Node = 'Q'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.847 ns" { Q~reg0 Q } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 57.39 % " "Info: Total cell delay = 1.634 ns ( 57.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.213 ns 42.61 % " "Info: Total interconnect delay = 1.213 ns ( 42.61 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.847 ns" { Q~reg0 Q } "NODE_NAME" } } }  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.847 ns" { Q~reg0 Q } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Q~reg0 D CLK -2.412 ns register " "Info: th for register Q~reg0 (data pin = D, clock pin = CLK) is -2.412 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.303 ns + Longest register " "Info: + Longest clock path from clock CLK to destination register is 2.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.547 ns) 2.303 ns Q~reg0 2 REG LC_X1_Y1_N2 1 " "Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "1.173 ns" { CLK Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 72.82 % " "Info: Total cell delay = 1.677 ns ( 72.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.626 ns 27.18 % " "Info: Total interconnect delay = 0.626 ns ( 27.18 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.727 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.727 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns D 1 PIN Pin_25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_25; Fanout = 1; PIN Node = 'D'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { D } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.508 ns) + CELL(0.089 ns) 4.727 ns Q~reg0 2 REG LC_X1_Y1_N2 1 " "Info: 2: + IC(3.508 ns) + CELL(0.089 ns) = 4.727 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "3.597 ns" { D Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.219 ns 25.79 % " "Info: Total cell delay = 1.219 ns ( 25.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.508 ns 74.21 % " "Info: Total interconnect delay = 3.508 ns ( 74.21 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "4.727 ns" { D Q~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "4.727 ns" { D Q~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK Q Q~reg0 5.323 ns register " "Info: Minimum tco from clock CLK to destination pin Q through register Q~reg0 is 5.323 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.303 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 2.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.547 ns) 2.303 ns Q~reg0 2 REG LC_X1_Y1_N2 1 " "Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "1.173 ns" { CLK Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 72.82 % " "Info: Total cell delay = 1.677 ns ( 72.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.626 ns 27.18 % " "Info: Total interconnect delay = 0.626 ns ( 27.18 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.847 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.847 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q~reg0 1 REG LC_X1_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(1.634 ns) 2.847 ns Q 2 PIN Pin_22 0 " "Info: 2: + IC(1.213 ns) + CELL(1.634 ns) = 2.847 ns; Loc. = Pin_22; Fanout = 0; PIN Node = 'Q'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.847 ns" { Q~reg0 Q } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 57.39 % " "Info: Total cell delay = 1.634 ns ( 57.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.213 ns 42.61 % " "Info: Total interconnect delay = 1.213 ns ( 42.61 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.847 ns" { Q~reg0 Q } "NODE_NAME" } } }  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.847 ns" { Q~reg0 Q } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 21 16:50:40 2006 " "Info: Processing ended: Thu Dec 21 16:50:40 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}