dcfq.tan.qmsg

经典触发器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 21 16:50:40 2006 " "Info: Processing started: Thu Dec 21 16:50:40 2006" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off DCFQ -c DCFQ --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off DCFQ -c DCFQ --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 6 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register paths exist for clock CLK" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "Q~reg0 D CLK 2.453 ns register " "Info: tsu for register Q~reg0 (data pin = D, clock pin = CLK) is 2.453 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.727 ns + Longest pin register " "Info: + Longest pin to register delay is 4.727 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns D 1 PIN Pin_25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_25; Fanout = 1; PIN Node = 'D'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { D } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.508 ns) + CELL(0.089 ns) 4.727 ns Q~reg0 2 REG LC_X1_Y1_N2 1 " "Info: 2: + IC(3.508 ns) + CELL(0.089 ns) = 4.727 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "3.597 ns" { D Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.219 ns 25.79 % " "Info: Total cell delay = 1.219 ns ( 25.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.508 ns 74.21 % " "Info: Total interconnect delay = 3.508 ns ( 74.21 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "4.727 ns" { D Q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.303 ns - Shortest register " "Info: - Shortest clock path from clock CLK to destination register is 2.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.547 ns) 2.303 ns Q~reg0 2 REG LC_X1_Y1_N2 1 " "Info: 2: + IC(0.626 ns) + CELL(0.547 ns) = 2.303 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "1.173 ns" { CLK Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/DCFQ.vhd" "" "" { Text "d:/quartus/dcfq项目/DCFQ.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 72.82 % " "Info: Total cell delay = 1.677 ns ( 72.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.626 ns 27.18 % " "Info: Total interconnect delay = 0.626 ns ( 27.18 % )" {  } {  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "4.727 ns" { D Q~reg0 } "NODE_NAME" } } } { "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" "" "" { Report "d:/quartus/dcfq项目/db/DCFQ_cmp.qrpt" Compiler "DCFQ" "UNKNOWN" "V1" "d:/quartus/dcfq项目/db/DCFQ.quartus_db" { Floorplan "" "" "2.303 ns" { CLK Q~reg0 } "NODE_NAME" } } }  } 0}